Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc: add FPGA device and System clock to logs.

This commit is contained in:
Florent Kermarrec 2020-03-10 11:10:23 +01:00
parent 02cba41d64
commit 04b8a91255
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/integration/soc.py
View File

@ -661,6 +661,8 @@ class SoC(Module):
self.logger.info(colorer("-"*80, color="bright")) self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Creating SoC... ({})".format(build_time()))) self.logger.info(colorer("Creating SoC... ({})".format(build_time())))
self.logger.info(colorer("-"*80, color="bright")) self.logger.info(colorer("-"*80, color="bright"))
self.logger.info("FPGA device : {}.".format(platform.device))
self.logger.info("System clock: {:3.2f}MHz.".format(sys_clk_freq/1e6))
# SoC attributes --------------------------------------------------------------------------- # SoC attributes ---------------------------------------------------------------------------
self.platform = platform self.platform = platform