simplify litescope export with do_exit call and remove automatic clean
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parent
989cca24bc
commit
04f7fbd7e2
8
make.py
8
make.py
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@ -111,15 +111,14 @@ RLE: {}
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str(soc.la.with_rle)
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str(soc.la.with_rle)
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)
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)
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)
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)
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# dependencies
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# dependencies
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if actions["all"]:
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if actions["all"]:
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actions["clean"] = True
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actions["build-csr-csv"] = True
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actions["build-csr-csv"] = True
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actions["build-bitstream"] = True
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actions["build-bitstream"] = True
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actions["load-bitstream"] = True
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actions["load-bitstream"] = True
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if actions["build-bitstream"]:
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if actions["build-bitstream"]:
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actions["clean"] = True
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actions["build-csr-csv"] = True
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actions["build-csr-csv"] = True
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actions["build-bitstream"] = True
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actions["build-bitstream"] = True
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actions["load-bitstream"] = True
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actions["load-bitstream"] = True
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@ -132,7 +131,10 @@ RLE: {}
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write_to_file(args.csr_csv, csr_csv)
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write_to_file(args.csr_csv, csr_csv)
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if actions["build-bitstream"]:
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if actions["build-bitstream"]:
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platform.build(soc, build_name=build_name)
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vns = platform.build(soc, build_name=build_name)
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if hasattr(soc, "do_exit") and vns is not None:
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if hasattr(soc.do_exit, '__call__'):
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soc.do_exit(vns)
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if actions["load-bitstream"]:
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if actions["load-bitstream"]:
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prog = platform.create_programmer()
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prog = platform.create_programmer()
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@ -1,4 +1,4 @@
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import os, atexit
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import os
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from migen.bank import csrgen
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone, csr
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@ -99,10 +99,8 @@ class LiteScopeSoC(GenSoC, AutoCSR):
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)
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)
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self.submodules.la = LiteScopeLA(self.debug, 512, with_subsampler=True)
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self.submodules.la = LiteScopeLA(self.debug, 512, with_subsampler=True)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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atexit.register(self.exit, platform)
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def exit(self, platform):
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def do_exit(self, vns):
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if platform.vns is not None:
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self.la.export(vns, "test/la.csv")
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self.la.export(platform.vns, "./test/la.csv")
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default_subtarget = LiteScopeSoC
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default_subtarget = LiteScopeSoC
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