CHANGES: update.

2020-07-28 18:37:23 +02:00 · 2020-07-28 18:37:23 +02:00 · 0696b409ab
parent fe38e12b21
commit 0696b409ab
1 changed files with 1 additions and 0 deletions
--- a/1
+++ b/1
@ -27,6 +27,7 @@
 	- Revert to a single crt0 (avoid ctr/xip variants).
 	- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
 	- Add AXI-Lite bus standard support.
+	- Add VexRiscv SMP CPU support.

 	[> API changes/Deprecation
 	--------------------------