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CHANGES: update.

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Florent Kermarrec 2020-07-28 18:37:23 +02:00
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commit 0696b409ab
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@ -27,6 +27,7 @@
- Revert to a single crt0 (avoid ctr/xip variants).
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
- Add AXI-Lite bus standard support.
- Add VexRiscv SMP CPU support.
[> API changes/Deprecation
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