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cores/cpu/vexiiriscv: Add PMP support 

The RISC-V PMP feature can now be enabled via --vexii-args="--pmp-size=8" for instance.

TOR support can be disabled via --pmp-tor-disable to save area / timings
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Dolu1990 2024-11-26 17:40:03 +01:00 committed by GitHub
parent 29c5a1db83
commit 070c4cd387
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litex/soc/cores/cpu/vexiiriscv/core.py
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@ -156,7 +156,7 @@ class VexiiRiscv(CPU):
vdir = get_data_mod("cpu", "vexiiriscv").data_location vdir = get_data_mod("cpu", "vexiiriscv").data_location
ndir = os.path.join(vdir, "ext", "VexiiRiscv") ndir = os.path.join(vdir, "ext", "VexiiRiscv")
NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "ca10ab58", args.update_repo) NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "b4269ddc", args.update_repo)
if not args.cpu_variant: if not args.cpu_variant:
args.cpu_variant = "standard" args.cpu_variant = "standard"