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litesata: fix permissions and imports

This commit is contained in:
Sebastien Bourdeauducq 2015-03-04 00:46:24 +00:00
parent 7c058a52c9
commit 073641faa1
3 changed files with 2 additions and 2 deletions
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0
misoclib/mem/litesata/example_designs/build/.keep_me Normal file
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0
misoclib/mem/litesata/example_designs/make.py Normal file → Executable file
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4
misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
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@ -1,6 +1,6 @@
from mibuild.generic_platform import *
from mibuild.xilinx_common import CRG_DS
from mibuild.xilinx_vivado import XilinxVivadoPlatform
from mibuild.xilinx.common import CRG_DS
from mibuild.xilinx.vivado import XilinxVivadoPlatform
_io = [
("sys_clk", 0, Pins("X")),