Use meaningful class names
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d3d5b481fe
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@ -1,8 +1,8 @@
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from migen.fhdl import verilog
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from migen.corelogic import divider
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d1 = divider.Inst(16)
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d2 = divider.Inst(16)
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d1 = divider.Divider(16)
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d2 = divider.Divider(16)
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frag = d1.get_fragment() + d2.get_fragment()
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o = verilog.convert(frag, {
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d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
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@ -29,7 +29,7 @@ class Arbiter:
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def __init__(self, masters, target):
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self.masters = masters
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self.target = target
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self.rr = roundrobin.Inst(len(self.masters))
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self.rr = roundrobin.RoundRobin(len(self.masters))
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def get_fragment(self):
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comb = []
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@ -3,11 +3,11 @@ from migen.bus import csr
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from migen.fhdl.structure import *
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from migen.corelogic import timeline
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class Inst():
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class WB2CSR():
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def __init__(self):
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self.wishbone = wishbone.Slave("to_csr")
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self.csr = csr.Master("from_wishbone")
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self.timeline = timeline.Inst(self.wishbone.cyc_i & self.wishbone.stb_i,
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self.timeline = timeline.Timeline(self.wishbone.cyc_i & self.wishbone.stb_i,
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[(1, [self.csr.we_o.eq(self.wishbone.we_i)]),
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(2, [self.wishbone.ack_o.eq(1)]),
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(3, [self.wishbone.ack_o.eq(0)])])
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@ -1,6 +1,6 @@
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from migen.fhdl.structure import *
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class Inst:
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class Divider:
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def __init__(self, w):
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self.w = w
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@ -1,6 +1,6 @@
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from migen.fhdl.structure import *
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class Inst:
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class RoundRobin:
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def __init__(self, n):
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self.n = n
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self.bn = bits_for(self.n-1)
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@ -1,6 +1,6 @@
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from migen.fhdl.structure import *
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class Inst:
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class Timeline:
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def __init__(self, trigger, events):
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self.trigger = trigger
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self.events = events
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@ -60,7 +60,7 @@ class NE(_SimpleBinary):
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class DivMod(Actor):
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def __init__(self, width):
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self.div = divider.Inst(width)
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self.div = divider.Divider(width)
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Actor.__init__(self,
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SchedulingModel(SchedulingModel.SEQUENTIAL, width),
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("operands", Sink, [("dividend", self.div.dividend_i), ("divisor", self.div.divisor_i)]),
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