Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed 

Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
cc003bef3a
and litex bumped to 4a18b828bc,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
This commit is contained in:
Jędrzej Boczar 2020-07-20 15:17:56 +02:00
parent 4a18b828bc
commit 07bc589c41
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
litex/soc/integration/soc.py
View File

@ -282,12 +282,15 @@ class SoCBusHandler(Module):
assert direction in ["m2s", "s2m"] assert direction in ["m2s", "s2m"]
if isinstance(interface, wishbone.Interface): if isinstance(interface, wishbone.Interface):
new_interface = wishbone.Interface(data_width=self.data_width) if interface.data_width != self.data_width:
if direction == "m2s": new_interface = wishbone.Interface(data_width=self.data_width)
converter = wishbone.Converter(master=interface, slave=new_interface) if direction == "m2s":
if direction == "s2m": converter = wishbone.Converter(master=interface, slave=new_interface)
converter = wishbone.Converter(master=new_interface, slave=interface) if direction == "s2m":
self.submodules += converter converter = wishbone.Converter(master=new_interface, slave=interface)
self.submodules += converter
else:
new_interface = interface
elif isinstance(interface, axi.AXILiteInterface): elif isinstance(interface, axi.AXILiteInterface):
# Data width conversion # Data width conversion
intermediate = axi.AXILiteInterface(data_width=self.data_width) intermediate = axi.AXILiteInterface(data_width=self.data_width)