interconnect/wishbone: check err in simulation
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parent
416f1b4281
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07cfda119d
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@ -90,6 +90,8 @@ class Interface(Record):
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yield self.bte.eq(bte)
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yield self.bte.eq(bte)
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yield self.we.eq(1)
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yield self.we.eq(1)
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yield from self._do_transaction()
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yield from self._do_transaction()
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if (yield self.err):
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raise ValueError("bus error")
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def read(self, adr, cti=None, bte=None):
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def read(self, adr, cti=None, bte=None):
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yield self.adr.eq(adr)
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yield self.adr.eq(adr)
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@ -99,6 +101,8 @@ class Interface(Record):
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if bte is not None:
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if bte is not None:
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yield self.bte.eq(bte)
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yield self.bte.eq(bte)
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yield from self._do_transaction()
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yield from self._do_transaction()
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if (yield self.err):
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raise ValueError("bus error")
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return (yield self.dat_r)
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return (yield self.dat_r)
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def get_ios(self, bus_name="wb"):
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def get_ios(self, bus_name="wb"):
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