global clean up
- remove initial sims - remove SATAPHYDeviceCtrl - rename to LiteSATA - rename test to bist
This commit is contained in:
Florent Kermarrec
parent
e90d97e9c2
commit
083bd54121
2
Makefile
2
Makefile
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@ -5,7 +5,7 @@ TOOLCHAIN = vivado
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PLATFORM = kc705
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PROGRAMMER = vivado
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CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -Op programmer $(PROGRAMMER) -p $(PLATFORM) -t test
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CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -Op programmer $(PROGRAMMER) -p $(PLATFORM) -t bist
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csv:
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cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv -Ot export_mila True
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66
README
66
README
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@ -1,31 +1,57 @@
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_____ _ ____ _ _ _ _
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| __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
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| __| | | | . | | | | | | | . | | _| .'| |
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|_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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|___| |___| |___|
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Copyright 2014 / Florent Kermarrec / florent@enjoy-digital.fr
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Kintex-7 SATA PHY for M-Labs
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--------------------------------------------------------------------------------
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__ _ __ _______ _________
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/ / (_) /____ / __/ _ /_ __/ _ |
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/ /__/ / __/ -_)\ \/ __ |/ / / __ |
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/____/_/\__/\__/___/_/ |_/_/ /_/ |_|
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Copyright 2014-2015 / Florent Kermarrec / florent@enjoy-digital.fr
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A lite open-source SATA1/2/3 controller
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developed in partnership with M-Labs Ltd / HKU
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--------------------------------------------------------------------------------
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[> Getting started
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------------------
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1. Obtain MiSoC and follow its "Quick start guide". Set the MSCDIR environment
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variable to the MiSoC directory.
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1. Install Python3 and Xilinx's Vivado software.
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2. Build design:
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2. Obtain Migen and install it:
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git clone https://github.com/enjoy-digital/migen
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cd migen
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python3 setup.py install
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cd ..
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3. Obtain Miscope and install it:
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git clone https://github.com/enjoy-digital/miscope
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cd miscope
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python3 setup.py install
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cd ..
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4. Obtain MiSoC:
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git clone https://github.com/enjoy-digital/misoc --recursive
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5. Copy lite-sata in working directory and move to it.
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6. Build and load design:
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make all
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3. Load design:
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make load
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4. Run test:
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make test
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7. Test design:
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go to test directory
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python3 bist.py
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[> Cores :
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- UART2Wishbone bridge
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- SATA PHY
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[> Simulations :
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Simulation are avalaible in ./lib/sata/test:
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- crc_tb
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- scrambler_tb
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- phy_datapath_tb
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- link_tb
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- command_tb
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- bist_tb
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hdd.py is a HDD model with implementing all SATA layers.
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To run a simulation, move to the simulation directory and run:
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make simulation_name
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[> Tests :
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A synthetisable BIST is provided. It can be controled with ./test/bist.py
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[> Contact
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E-mail: florent@enjoy-digital.fr
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@ -4,6 +4,7 @@ from lib.sata.phy.datapath import SATAPHYDatapath
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class SATAPHY(Module):
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def __init__(self, pads, clk_freq, host=True, device_family="k7", speed="SATA1"):
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self.speed = speed
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# Transceiver / Clocks
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if device_family == "k7":
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from lib.sata.phy.k7.trx import K7SATAPHYTRX
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@ -163,113 +163,3 @@ class SATAPHYHostCtrl(Module):
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)
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)
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)
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# Note : Tested only in simulation
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class SATAPHYDeviceCtrl(Module):
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def __init__(self, trx, crg, clk_freq):
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self.ready = Signal()
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sink = Sink(phy_description(32))
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source = Source(phy_description(32))
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###
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self.comb += [
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source.stb.eq(1),
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sink.ack.eq(1)
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]
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retry_timeout = SATAPHYHostCtrlTimeout(us(10000, clk_freq))
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align_timeout = SATAPHYHostCtrlTimeout(us(873, clk_freq))
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self.submodules += align_timeout, retry_timeout
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self.fsm = fsm = FSM(reset_state="RESET")
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fsm.act("RESET",
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trx.tx_idle.eq(1),
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retry_timeout.load.eq(1),
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align_timeout.load.eq(1),
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If(crg.ready,
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NextState("AWAIT_COMINIT")
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)
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)
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fsm.act("AWAIT_COMINIT",
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trx.tx_idle.eq(1),
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If(trx.rx_cominit_stb,
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NextState("AWAIT_NO_COMINIT")
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)
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)
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fsm.act("AWAIT_NO_COMINIT",
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trx.tx_idle.eq(1),
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If(~trx.rx_cominit_stb,
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NextState("COMINIT")
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)
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)
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fsm.act("COMINIT",
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trx.tx_idle.eq(1),
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trx.tx_cominit_stb.eq(1),
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If(trx.tx_cominit_ack,
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NextState("AWAIT_COMWAKE")
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)
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)
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fsm.act("AWAIT_COMWAKE",
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trx.tx_idle.eq(1),
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retry_timeout.dec.eq(1),
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If(trx.rx_comwake_stb,
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NextState("AWAIT_NO_COMWAKE")
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).Else(
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If(retry_timeout.reached,
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NextState("RESET")
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)
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)
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)
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fsm.act("AWAIT_NO_COMWAKE",
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trx.tx_idle.eq(1),
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If(~trx.rx_comwake_stb,
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NextState("CALIBRATE")
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)
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)
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fsm.act("CALIBRATE",
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trx.tx_idle.eq(1),
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NextState("COMWAKE")
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)
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fsm.act("COMWAKE",
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trx.tx_idle.eq(1),
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trx.tx_comwake_stb.eq(1),
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If(trx.tx_comwake_stb,
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NextState("RESET_CRG"),
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crg.reset.eq(1),
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)
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)
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fsm.act("RESET_CRG",
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trx.tx_idle.eq(0),
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If(crg.ready,
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NextState("SEND_ALIGN")
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)
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)
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fsm.act("SEND_ALIGN",
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trx.tx_idle.eq(0),
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trx.rx_align.eq(1),
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source.data.eq(primitives["ALIGN"]),
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source.charisk.eq(0b0001),
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align_timeout.dec.eq(1),
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If(align_detect,
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NextState("READY")
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).Elif(align_timeout.reached,
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NextState("ERROR")
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)
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)
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fsm.act("READY",
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trx.tx_idle.eq(0),
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NextState("READY"),
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If(trx.rx_idle,
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NextState("RESET")
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),
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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trx.tx_idle.eq(1),
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NextState("RESET")
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)
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self.comb += \
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align_detect.eq(sink.stb & (sink.data == primitives["ALIGN"]))
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@ -1,11 +0,0 @@
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##############################################################################
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#
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# Compilation of SoC RTL files
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#
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##############################################################################
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set HDL_WORK "work"
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hdl_compile -v 2005 {
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../../misoc/build/simdesign-kc705.v
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}
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@ -1,8 +0,0 @@
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##############################################################################
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#
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# Compilation of MiSoC TB files
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#
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##############################################################################
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hdl_compile -sim glbl.v
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hdl_compile -sim top_tb.v
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66
sim/glbl.v
66
sim/glbl.v
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@ -1,66 +0,0 @@
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $
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`timescale 1 ps / 1 ps
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module glbl ();
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parameter ROC_WIDTH = 100000;
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parameter TOC_WIDTH = 0;
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//-------- STARTUP Globals --------------
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wire GSR;
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wire GTS;
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wire GWE;
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wire PRLD;
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tri1 p_up_tmp;
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tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
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wire PROGB_GLBL;
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wire CCLKO_GLBL;
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reg GSR_int;
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reg GTS_int;
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reg PRLD_int;
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//-------- JTAG Globals --------------
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wire JTAG_TDO_GLBL;
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wire JTAG_TCK_GLBL;
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wire JTAG_TDI_GLBL;
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wire JTAG_TMS_GLBL;
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wire JTAG_TRST_GLBL;
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reg JTAG_CAPTURE_GLBL;
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reg JTAG_RESET_GLBL;
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reg JTAG_SHIFT_GLBL;
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reg JTAG_UPDATE_GLBL;
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reg JTAG_RUNTEST_GLBL;
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reg JTAG_SEL1_GLBL = 0;
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reg JTAG_SEL2_GLBL = 0 ;
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reg JTAG_SEL3_GLBL = 0;
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reg JTAG_SEL4_GLBL = 0;
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reg JTAG_USER_TDO1_GLBL = 1'bz;
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reg JTAG_USER_TDO2_GLBL = 1'bz;
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reg JTAG_USER_TDO3_GLBL = 1'bz;
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reg JTAG_USER_TDO4_GLBL = 1'bz;
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assign (weak1, weak0) GSR = GSR_int;
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assign (weak1, weak0) GTS = GTS_int;
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assign (weak1, weak0) PRLD = PRLD_int;
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initial begin
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GSR_int = 1'b1;
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PRLD_int = 1'b1;
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#(ROC_WIDTH)
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GSR_int = 1'b0;
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PRLD_int = 1'b0;
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end
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initial begin
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GTS_int = 1'b1;
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#(TOC_WIDTH)
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GTS_int = 1'b0;
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end
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endmodule
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@ -1,29 +0,0 @@
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set HDL_TOOLTYPE SIMULATION
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set HDL_TOOLNAME 0in
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set HDL_PUTS puts
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set HDL_MSG_FORMAT "********** %s **********"
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proc hdl_tool_library {lib} {
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}
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proc hdl_tool_compile {format version incdirs library define files behavioral} {
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set command analyze
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lappend command -work [string tolower $library]
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switch $format {
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"vhdl" {
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lappend command -vhdl
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}
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"verilog" {
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foreach d $define {
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lappend command +define+$d
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}
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foreach i $incdirs {
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lappend command +incdir+$i
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}
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}
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}
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foreach f $files {
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lappend command $f
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}
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puts [eval $command]
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}
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@ -1,406 +0,0 @@
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##############################################################################
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# Define some global variables
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##############################################################################
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if {![info exists HDL_LIBRARIES]} {
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set HDL_LIBRARIES ()
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}
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set HDL_TARGET "default_target"
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set HDL_PATH [pwd]
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set HDL_WORK "work"
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# Uncomment the following line to generate a log file for debug
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#set HDL_LOG [open "hdl_common.log" "w"]
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|
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##############################################################################
|
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# Some utilities
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||||
##############################################################################
|
||||
|
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# Extract first element from a list (for argument processing)
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proc extract_first {list_name {option ""}} {
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upvar $list_name mylist
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if {[string length $option]>0 && [llength $mylist]==0} {
|
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error "Missing argument for option $option"
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||||
}
|
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set first [lindex $mylist 0]
|
||||
if {[string length $option]>0 && [string match "-*" $first]} {
|
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error "Missing argument for option $option"
|
||||
}
|
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set mylist [lrange $mylist 1 end]
|
||||
return $first
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}
|
||||
|
||||
# Clean-up file path
|
||||
proc clean_path {f} {
|
||||
# Add trailing /
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||||
set f "$f/"
|
||||
# Remove double / (excepted leading)
|
||||
while {[regsub {(.)//} $f "\1/" f]} {}
|
||||
# Remove .
|
||||
while {[regsub {/\./} $f "/" f]} {}
|
||||
# Remove ..
|
||||
while {[regsub {/[^/.]+/\.\./} $f "/" f]} {}
|
||||
# Remove trailing /
|
||||
regsub {/$} $f "" f
|
||||
return $f
|
||||
}
|
||||
|
||||
# Translate relative paths to absolute paths
|
||||
proc get_full_path {files} {
|
||||
global HDL_PATH
|
||||
set r {}
|
||||
# For DOS paths, replace \ by /
|
||||
regsub -all {\\} $files "/" files
|
||||
foreach f $files {
|
||||
hdl_debug " $f"
|
||||
# Append file path
|
||||
if {[string match "/*" $f] || [string match "?:/*" $f]} {
|
||||
# Path is an absolute path
|
||||
hdl_warning "Using absolute path $f"
|
||||
} else {
|
||||
# Path is a relative path
|
||||
set f [clean_path $HDL_PATH/$f]
|
||||
}
|
||||
hdl_debug " => $f"
|
||||
lappend r $f
|
||||
# Check access to file
|
||||
if {![file readable $f]} {
|
||||
error "Cannot read file $f"
|
||||
}
|
||||
}
|
||||
return $r
|
||||
}
|
||||
|
||||
# Check if value match any pattern in the list
|
||||
proc match_list {mlist value} {
|
||||
set match 0
|
||||
foreach m $mlist {
|
||||
if [string match $m $value] {
|
||||
set match 1
|
||||
}
|
||||
}
|
||||
return $match
|
||||
}
|
||||
|
||||
proc get_lib_path {} {
|
||||
if [file isdirectory "/cad/trash"] {
|
||||
set libs "/cad/trash[pwd]/libs"
|
||||
} elseif [file isdirectory "e:/trash"] {
|
||||
set libs [pwd]
|
||||
# Replace D:/ by D/ for local drive
|
||||
regsub ":" $libs "" libs
|
||||
# Remove leading // for network drive
|
||||
regsub "//" $libs "" libs
|
||||
set libs "e:/trash/$libs"
|
||||
} else {
|
||||
# No "trash" directory on this machine => work locally
|
||||
set libs "./libs"
|
||||
}
|
||||
file mkdir $libs
|
||||
return $libs
|
||||
}
|
||||
|
||||
##############################################################################
|
||||
# Procedures to display messages
|
||||
##############################################################################
|
||||
|
||||
# Write message to log file if logging enabled
|
||||
proc hdl_log { msg } {
|
||||
global HDL_LOG
|
||||
if [info exists HDL_LOG] {
|
||||
puts $HDL_LOG $msg
|
||||
flush $HDL_LOG
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
# Debug messages are sent only to log file
|
||||
proc hdl_debug { msg } {
|
||||
hdl_log "hdl_common - Debug: $msg"
|
||||
return
|
||||
}
|
||||
|
||||
# According to the tool, "puts" or "echo" should be used
|
||||
# HDL_PUTS variable is used for this purpose
|
||||
# All message are also sent to log file
|
||||
proc hdl_puts { msg } {
|
||||
global HDL_PUTS
|
||||
$HDL_PUTS $msg
|
||||
hdl_log $msg
|
||||
return
|
||||
}
|
||||
|
||||
proc hdl_note { msg } {
|
||||
hdl_puts "hdl_common - Note: $msg"
|
||||
return
|
||||
}
|
||||
|
||||
proc hdl_warning { msg } {
|
||||
hdl_puts "hdl_common - Warning: $msg"
|
||||
return
|
||||
}
|
||||
|
||||
proc hdl_message { args } {
|
||||
global HDL_MSG_FORMAT
|
||||
hdl_puts [format $HDL_MSG_FORMAT [join $args " "]]
|
||||
return
|
||||
}
|
||||
|
||||
##############################################################################
|
||||
# Procedures for compilation scripts
|
||||
##############################################################################
|
||||
|
||||
# Compile source files
|
||||
proc hdl_compile { args } {
|
||||
global HDL_TOOLTYPE HDL_TOOLNAME HDL_TARGET HDL_LIBRARIES HDL_WORK
|
||||
# Default values
|
||||
set format ""
|
||||
set version "93"
|
||||
set files {}
|
||||
set incdirs {}
|
||||
set only_for {}
|
||||
set not_for {}
|
||||
set toolname {}
|
||||
set tooltype "*"
|
||||
set library $HDL_WORK
|
||||
set define {}
|
||||
set behavioral 0
|
||||
|
||||
# Decode arguments
|
||||
while {[llength $args]} {
|
||||
set arg [extract_first args]
|
||||
switch -glob -- $arg {
|
||||
"-f" {
|
||||
set format [extract_first args "-f"]
|
||||
}
|
||||
"-v" {
|
||||
set version [extract_first args "-version"]
|
||||
}
|
||||
"-only_for" {
|
||||
set only_for [concat $only_for [extract_first args "-only_for"]]
|
||||
}
|
||||
"-not_for" {
|
||||
set not_for [concat $not_for [extract_first args "-not_for"]]
|
||||
}
|
||||
"-sim" {
|
||||
set tooltype "SIMULATION"
|
||||
set behavioral 1
|
||||
}
|
||||
"-syn" {
|
||||
set tooltype "SYNTHESIS"
|
||||
set behavioral 0
|
||||
}
|
||||
"-tool" {
|
||||
set toolname [concat $toolname [extract_first args "-tool"]]
|
||||
}
|
||||
"-incdir" {
|
||||
set incdirs [concat $incdirs [extract_first args "-incdir"]]
|
||||
}
|
||||
"-lib" {
|
||||
set library [extract_first args "-lib"]
|
||||
if {[string match "work" $library]} {
|
||||
hdl_warning "Specifying '-lib work' is useless"
|
||||
}
|
||||
}
|
||||
"-define" {
|
||||
set define [concat $define [extract_first args "-define"]]
|
||||
}
|
||||
"-*" {
|
||||
error "Unsupported argument $arg"
|
||||
}
|
||||
default {
|
||||
set files [concat $files $arg]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Check arguments
|
||||
if {![llength $files]} {
|
||||
error "No file to compile"
|
||||
}
|
||||
# If no "-only_for" option given, use file for any target
|
||||
if {[llength $only_for]==0} {
|
||||
set only_for {*}
|
||||
}
|
||||
# If no "-tool" option given, use file for any tool
|
||||
if {[llength $toolname]==0} {
|
||||
set toolname {*}
|
||||
}
|
||||
|
||||
# Check if compilation is required
|
||||
if {[match_list $only_for $HDL_TARGET] && ![match_list $not_for $HDL_TARGET] &&
|
||||
[string match $tooltype $HDL_TOOLTYPE] && [match_list $toolname $HDL_TOOLNAME]} {
|
||||
# Create library if needed
|
||||
if {[lsearch -exact $HDL_LIBRARIES $library]<0} {
|
||||
hdl_note "Creating library $library"
|
||||
lappend HDL_LIBRARIES $library
|
||||
hdl_tool_library $library
|
||||
}
|
||||
# Compile files
|
||||
foreach f $files {
|
||||
# Warning if dummy file is used
|
||||
if {[string match "*dummy*" [string tolower $f]]} {
|
||||
hdl_note "Using [file tail $f]"
|
||||
}
|
||||
# Determine format
|
||||
if {![llength $format]} {
|
||||
if {[string match "*.vh?*" $f]} {
|
||||
set format "vhdl"
|
||||
} elseif {[string match "*.v*" $f]} {
|
||||
set format "verilog"
|
||||
set version "sv"
|
||||
} elseif {[string match "*.sv" $f]} {
|
||||
set format "verilog"
|
||||
set version "sv"
|
||||
}
|
||||
}
|
||||
}
|
||||
hdl_tool_compile $format $version [get_full_path $incdirs] $library $define [get_full_path $files] $behavioral
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
# Change directory
|
||||
proc hdl_cd { path } {
|
||||
global HDL_PATH
|
||||
set HDL_PATH [get_full_path $path]
|
||||
hdl_debug "New path is $HDL_PATH"
|
||||
return
|
||||
}
|
||||
|
||||
# Execute script
|
||||
proc hdl_source { args } {
|
||||
global HDL_PATH HDL_TARGET HDL_WORK HDL_TOOLTYPE HDL_TOOLNAME
|
||||
# Save original values
|
||||
set save_path $HDL_PATH
|
||||
set save_target $HDL_TARGET
|
||||
set save_work $HDL_WORK
|
||||
# Default value
|
||||
set files {}
|
||||
set toolname {}
|
||||
set tooltype "*"
|
||||
set only_for {}
|
||||
set not_for {}
|
||||
# Process options
|
||||
while {[llength $args]} {
|
||||
set arg [extract_first args]
|
||||
switch -glob -- $arg {
|
||||
"-lib" {
|
||||
set HDL_WORK [extract_first args "-lib"]
|
||||
if {[string match "work" $HDL_WORK]} {
|
||||
hdl_warning "Specifying '-lib work' is useless"
|
||||
}
|
||||
}
|
||||
"-target" {
|
||||
set HDL_TARGET [extract_first args "-target"]
|
||||
}
|
||||
"-sim" {
|
||||
set tooltype "SIMULATION"
|
||||
set behavioral 1
|
||||
}
|
||||
"-syn" {
|
||||
set tooltype "SYNTHESIS"
|
||||
set behavioral 0
|
||||
}
|
||||
"-tool" {
|
||||
set toolname [concat $toolname [extract_first args "-tool"]]
|
||||
}
|
||||
"-only_for" {
|
||||
set only_for [concat $only_for [extract_first args "-only_for"]]
|
||||
}
|
||||
"-not_for" {
|
||||
set not_for [concat $not_for [extract_first args "-not_for"]]
|
||||
}
|
||||
"-*" {
|
||||
error "Unsupported argument $arg"
|
||||
}
|
||||
default {
|
||||
set files [concat $files $arg]
|
||||
}
|
||||
}
|
||||
}
|
||||
# Check arguments
|
||||
if {![llength $files]} {
|
||||
error "No script specified"
|
||||
}
|
||||
# If no "-only_for" option given, use file for any target
|
||||
if {[llength $only_for]==0} {
|
||||
set only_for {*}
|
||||
}
|
||||
# If no "-tool" option given, use file for any tool
|
||||
if {[llength $toolname]==0} {
|
||||
set toolname {*}
|
||||
}
|
||||
|
||||
# Check if compilation is required
|
||||
if {[match_list $only_for $HDL_TARGET] && ![match_list $not_for $HDL_TARGET] &&
|
||||
[string match $tooltype $HDL_TOOLTYPE] && [match_list $toolname $HDL_TOOLNAME]} {
|
||||
# Source scripts
|
||||
foreach script $files {
|
||||
# Change directory to script location
|
||||
hdl_cd [file dirname $script]
|
||||
# Execute script
|
||||
set script [get_full_path [file tail $script]]
|
||||
hdl_note "Source $script ($HDL_TARGET)"
|
||||
uplevel source $script
|
||||
# Restore original path
|
||||
set HDL_PATH $save_path
|
||||
hdl_debug "Back to directory $HDL_PATH"
|
||||
}
|
||||
}
|
||||
# Restore original values
|
||||
set HDL_TARGET $save_target
|
||||
set HDL_WORK $save_work
|
||||
#puts "Back to $HDL_PATH"
|
||||
return
|
||||
}
|
||||
|
||||
# Specify target
|
||||
proc hdl_set_target { args } {
|
||||
global HDL_TARGET env
|
||||
# Default values
|
||||
set use_env 0
|
||||
set default ""
|
||||
set target ""
|
||||
# Decode arguments
|
||||
while {[llength $args]} {
|
||||
set arg [extract_first args]
|
||||
switch -glob -- $arg {
|
||||
"-env" {
|
||||
set use_env 1
|
||||
}
|
||||
"-default" {
|
||||
set default [extract_first args "-default"]
|
||||
}
|
||||
"-*" {
|
||||
error "Unsupported argument $arg"
|
||||
}
|
||||
default {
|
||||
set target $arg
|
||||
}
|
||||
}
|
||||
}
|
||||
# Check arguments
|
||||
if {[llength $target]} {
|
||||
set HDL_TARGET $target
|
||||
hdl_note "Using target $HDL_TARGET"
|
||||
} elseif {$use_env} {
|
||||
if {[info exists env(HDL_TARGET)]} {
|
||||
set HDL_TARGET $env(HDL_TARGET)
|
||||
hdl_note "Using target $HDL_TARGET (from environment variable HDL_TARGET)"
|
||||
} elseif {[llength $default]} {
|
||||
set HDL_TARGET $default
|
||||
hdl_note "Using default target $HDL_TARGET (environment variable HDL_TARGET not defined)"
|
||||
} else {
|
||||
error "No environment variable defined and no default target"
|
||||
}
|
||||
} else {
|
||||
error "Missing argument"
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
##############################################################################
|
||||
|
||||
# clock is an invalid command name for Synplify at least until version 2010.09
|
||||
# hdl_debug [clock format [clock seconds]]
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME formality
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "\n********** %s **********\n"
|
||||
|
||||
proc hdl_tool_library {lib} {
|
||||
define_design_lib $lib -path lib_$lib
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global search_path
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
# Add include paths
|
||||
set search_path [concat $incdirs $search_path]
|
||||
# Compile files
|
||||
foreach f $files {
|
||||
if {[string match $format "vhdl"]} {
|
||||
if {[string match $version "93"]} {
|
||||
read_vhdl -93 -libname $library $f
|
||||
} else {
|
||||
read_vhdl -libname $library $f
|
||||
}
|
||||
} else {
|
||||
read_verilog -01 -libname $library $f
|
||||
}
|
||||
puts ""
|
||||
}
|
||||
# Remove include paths
|
||||
set search_path [lrange $search_path [llength $incdirs] end]
|
||||
}
|
||||
|
|
@ -1,80 +0,0 @@
|
|||
# Set the option CHECK_SYNTHESIS to 1 if you want to have -check_synthesis in simulation. For now
|
||||
# tools like Modelsim generate too many false positives so it is disabled by default:
|
||||
|
||||
set CHECK_SYNTHESIS 0
|
||||
|
||||
set NO_DEBUG 0
|
||||
|
||||
set HDL_TOOLTYPE SIMULATION
|
||||
set HDL_TOOLNAME modelsim
|
||||
set HDL_PUTS echo
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
# Return the directory containing library lib
|
||||
proc getvmap {lib} {
|
||||
if {[catch {vmap $lib} result]} {
|
||||
# Library does not exist yet => default directory
|
||||
return $lib
|
||||
}
|
||||
set dir ""
|
||||
# Get directory returned by vmap
|
||||
regexp { maps to directory (.*)\.$} $result match dir
|
||||
return $dir
|
||||
}
|
||||
|
||||
proc hdl_tool_library {lib} {
|
||||
set lib [string tolower $lib]
|
||||
# Delete library
|
||||
set path [getvmap $lib]
|
||||
if {[file isdirectory $path]} {
|
||||
catch {
|
||||
vdel -lib $path -all
|
||||
}
|
||||
}
|
||||
# Create library
|
||||
set path [get_lib_path]/$lib
|
||||
vlib $path
|
||||
vmap $lib $path
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global CHECK_SYNTHESIS
|
||||
global NO_DEBUG
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
set command vcom
|
||||
if { $version == 87 } {
|
||||
lappend command -87
|
||||
} elseif { $version == 93 } {
|
||||
lappend command -93
|
||||
}
|
||||
# More strict for synthesizable modules
|
||||
if { ! $behavioral && $CHECK_SYNTHESIS } {
|
||||
lappend command -check_synthesis
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
set command vlog
|
||||
if {$version == "sv"} {
|
||||
lappend command -sv
|
||||
}
|
||||
lappend command -timescale "1ns/1ns"
|
||||
foreach d $define {
|
||||
lappend command +define+$d
|
||||
}
|
||||
foreach i $incdirs {
|
||||
lappend command +incdir+$i
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$NO_DEBUG} {
|
||||
lappend command -nodebug
|
||||
}
|
||||
lappend command -work [string tolower $library]
|
||||
lappend command -quiet
|
||||
foreach f $files {
|
||||
lappend command $f
|
||||
}
|
||||
puts -nonewline [eval $command]
|
||||
return
|
||||
}
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
set HDL_TOOLTYPE SIMULATION
|
||||
set HDL_TOOLNAME ncsim
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
if {![file exists hdl.var]} {
|
||||
hdl_note "Creating default hdl.var"
|
||||
exec echo "DEFINE WORK work" > hdl.var
|
||||
}
|
||||
|
||||
if {![file exists cds.lib]} {
|
||||
hdl_note "Creating default cds.lib"
|
||||
exec echo "# This file was created automatically by hdl_ncsim.tcl" > cds.lib
|
||||
exec echo "# You can edit this file" >> cds.lib
|
||||
exec echo "# Please add the libraries that are not handled by hdl_ncsim.tcl" >> cds.lib
|
||||
exec echo "# (for example the Xilinx libraries compiled with compxlib)" >> cds.lib
|
||||
exec echo {INCLUDE ${CDS_INST_DIR}/tools/inca/files/cds.lib} >> cds.lib
|
||||
}
|
||||
|
||||
proc no_matching_line {pattern file} {
|
||||
return [catch {exec grep -q $pattern $file}]
|
||||
}
|
||||
|
||||
if {[no_matching_line "^INCLUDE mycds.lib$" cds.lib]} {
|
||||
hdl_note "Including mycds.lib in cds.lib"
|
||||
exec echo "INCLUDE mycds.lib" >> cds.lib
|
||||
}
|
||||
|
||||
hdl_note "Clean-up mycds.lib"
|
||||
exec echo "# This file is written automatically by hdl_ncsim.tcl" > mycds.lib
|
||||
exec echo "# Do not edit this file" >> mycds.lib
|
||||
exec echo "# It will be overwritten at each compilation" >> mycds.lib
|
||||
|
||||
proc hdl_tool_library {lib} {
|
||||
set lib [string tolower $lib]
|
||||
set path [get_lib_path]/${lib}_nc
|
||||
exec echo "DEFINE $lib $path" >> mycds.lib
|
||||
exec touch $path
|
||||
exec rm -r $path
|
||||
exec mkdir $path
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
set command "ncvhdl"
|
||||
if {$version != 87} {
|
||||
lappend command -v93
|
||||
}
|
||||
# Less strict VHDL for behavioral modules
|
||||
if {$behavioral} {
|
||||
lappend command -relax
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
set command "ncvlog"
|
||||
if {$version == "sv"} {
|
||||
lappend command -sv
|
||||
}
|
||||
foreach d $define {
|
||||
lappend command -define $d
|
||||
}
|
||||
foreach i $incdirs {
|
||||
lappend command -incdir $i
|
||||
}
|
||||
}
|
||||
}
|
||||
lappend command -work [string tolower $library]
|
||||
lappend command -nocopyright
|
||||
foreach f $files {
|
||||
lappend command $f
|
||||
}
|
||||
eval $command
|
||||
}
|
||||
|
||||
# Allow launching NC-Sim tools directly in TCL
|
||||
proc ncvlog { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncvlog $args]
|
||||
}
|
||||
proc ncvhdl { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncvhdl $args]
|
||||
}
|
||||
proc ncelab { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncelab $args]
|
||||
}
|
||||
proc ncsdfc { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncsdfc $args]
|
||||
}
|
||||
proc ncsim { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncsim $args]
|
||||
}
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME QuartusII
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
#if {[llength $incdirs]} {
|
||||
# error "-incdir not yet supported"
|
||||
#}
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
foreach f $files {
|
||||
set_global_assignment -name VHDL_FILE $f -library $library
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
foreach d $define {
|
||||
set_global_assignment -name VERILOG_MACRO $d
|
||||
}
|
||||
foreach f $files {
|
||||
set_global_assignment -name VERILOG_FILE $f -library $library
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if { [catch { puts "Quartus hdl_common script" } ] } {
|
||||
# Disable puts for Quartus (doesn't work with the GUI since no stdout channel)
|
||||
proc hdl_puts { msg } {
|
||||
}
|
||||
}
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME synopsys
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "\n********** %s **********\n"
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
foreach l $lib_list {
|
||||
set path [get_lib_path]/$l
|
||||
sh touch $path
|
||||
sh rm -r $path
|
||||
sh mkdir $path
|
||||
define_design_lib $l -path $path
|
||||
}
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global search_path
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
# Add include paths
|
||||
set search_path [concat $incdirs $search_path]
|
||||
# Compile files
|
||||
foreach f $files {
|
||||
if {[string match $format "vhdl"]} {
|
||||
puts "Compiling source file $f"
|
||||
}
|
||||
analyze -format $format -work $library $f
|
||||
puts ""
|
||||
}
|
||||
# Remove include paths
|
||||
set search_path [lrange $search_path [llength $incdirs] end]
|
||||
}
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME synplify
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
foreach f $files {
|
||||
add_file -vhdl -lib $library $f
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
foreach i $incdirs {
|
||||
set_option -include_path "$i"
|
||||
}
|
||||
foreach f $files {
|
||||
add_file -verilog $f
|
||||
}
|
||||
}
|
||||
"ngc" {
|
||||
foreach i $incdirs {
|
||||
set_option -include_path "$i"
|
||||
}
|
||||
foreach f $files {
|
||||
add_file -xilinx $f
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME XST
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global PROJECT_FILE
|
||||
|
||||
# do not use append, based on http://wiki.tcl.tk/1241
|
||||
set projectfile [open $PROJECT_FILE {WRONLY CREAT APPEND}]
|
||||
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
if {[llength $incdirs]} {
|
||||
error "-incdirs not yet supported"
|
||||
}
|
||||
puts "checking format"
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
foreach f $files {
|
||||
puts $projectfile "vhdl $library $f"
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
foreach f $files {
|
||||
puts $projectfile "verilog $library $f"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
close $projectfile
|
||||
|
||||
}
|
||||
32
sim/sim.do
32
sim/sim.do
|
|
@ -1,32 +0,0 @@
|
|||
transcript on
|
||||
transcript file CustomTranscript
|
||||
|
||||
##############################################################################
|
||||
# Setup libraries
|
||||
vlib work
|
||||
vmap unisims_ver D:/Installs/Logiciels/Xilinx/ISE14.6/14.6/ISE_DS/ISE/verilog/mti_se/10.1c/nt/unisims_ver
|
||||
vmap secureip D:/Installs/Logiciels/Xilinx/ISE14.6/14.6/ISE_DS/ISE/verilog/mti_se/10.1c/nt/secureip
|
||||
|
||||
# Compile design
|
||||
##############################################################################
|
||||
|
||||
source hdl_common/hdl_common.tcl
|
||||
source hdl_common/hdl_modelsim.tcl
|
||||
|
||||
hdl_source compile_rtl.tcl
|
||||
hdl_source compile_tb.tcl
|
||||
|
||||
##############################################################################
|
||||
# Run simulation
|
||||
##############################################################################
|
||||
|
||||
vsim -t ps -L secureip -L unisims_ver -novopt glbl top_tb
|
||||
|
||||
set NumericStdNoWarnings 1
|
||||
set StdArithNoWarnings 1
|
||||
|
||||
log -r *
|
||||
do wave.do
|
||||
|
||||
onbreak {resume}
|
||||
run 2000us
|
||||
BIN
sim/sim.png
BIN
sim/sim.png
Binary file not shown.
|
Before Width: | Height: | Size: 24 KiB |
43
sim/top_tb.v
43
sim/top_tb.v
|
|
@ -1,43 +0,0 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
module top_tb();
|
||||
|
||||
reg refclk_p;
|
||||
wire refclk_n;
|
||||
initial refclk_p = 1'b1;
|
||||
always #3.33 refclk_p = ~refclk_p;
|
||||
assign refclk_n = ~refclk_p;
|
||||
|
||||
reg clk200_p;
|
||||
wire clk200_n;
|
||||
initial clk200_p = 1'b1;
|
||||
always #2.5 clk200_p = ~clk200_p;
|
||||
assign clk200_n = ~clk200_p;
|
||||
|
||||
wire sata_txp;
|
||||
wire sata_txn;
|
||||
wire sata_rxp;
|
||||
wire sata_rxn;
|
||||
|
||||
top dut(
|
||||
.serial_cts(1'b0),
|
||||
.serial_rts(1'b0),
|
||||
.serial_tx(),
|
||||
.serial_rx(1'b0),
|
||||
.clk200_p(clk200_p),
|
||||
.clk200_n(clk200_n),
|
||||
.sata_host_refclk_p(refclk_p),
|
||||
.sata_host_refclk_n(refclk_n),
|
||||
.sata_host_txp(sata_txp),
|
||||
.sata_host_txn(sata_txn),
|
||||
.sata_host_rxp(sata_rxp),
|
||||
.sata_host_rxn(sata_rxn),
|
||||
.sata_device_refclk_p(refclk_p),
|
||||
.sata_device_refclk_n(refclk_n),
|
||||
.sata_device_txp(sata_rxp),
|
||||
.sata_device_txn(sata_rxn),
|
||||
.sata_device_rxp(sata_txp),
|
||||
.sata_device_rxn(sata_txn)
|
||||
);
|
||||
|
||||
endmodule
|
||||
32
sim/wave.do
32
sim/wave.do
|
|
@ -1,32 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_host_source_payload_d
|
||||
add wave -noupdate /top_tb/dut/sataphy_host_source_stb
|
||||
add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_device_source_payload_d
|
||||
add wave -noupdate -radix hexadecimal /top_tb/dut/sataphy_device_source_stb
|
||||
add wave -noupdate -radix hexadecimal /top_tb/refclk_p
|
||||
add wave -noupdate -radix hexadecimal /top_tb/refclk_n
|
||||
add wave -noupdate -radix hexadecimal /top_tb/clk200_p
|
||||
add wave -noupdate -radix hexadecimal /top_tb/clk200_n
|
||||
add wave -noupdate -radix hexadecimal /top_tb/sata_txp
|
||||
add wave -noupdate -radix hexadecimal /top_tb/sata_txn
|
||||
add wave -noupdate -radix hexadecimal /top_tb/sata_rxp
|
||||
add wave -noupdate -radix hexadecimal /top_tb/sata_rxn
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {16623348 ps} 0} {{Cursor 2} {21767465 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 446
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {17730427 ps}
|
||||
|
|
@ -4,6 +4,7 @@ from migen.fhdl.std import *
|
|||
from migen.bank import csrgen
|
||||
from migen.bus import wishbone, csr
|
||||
from migen.bus import wishbone2csr
|
||||
from migen.genlib.cdc import *
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
from migen.bank.description import *
|
||||
|
||||
|
|
@ -15,8 +16,6 @@ from lib.sata.phy import SATAPHY
|
|||
from lib.sata import SATACON
|
||||
from lib.sata.bist import SATABIST, SATABISTControl
|
||||
|
||||
from migen.genlib.cdc import *
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, platform):
|
||||
self.cd_sys = ClockDomain()
|
||||
|
|
@ -38,7 +37,7 @@ class _CRG(Module):
|
|||
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
|
||||
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
|
||||
|
||||
# 100MHz
|
||||
# 166MHz
|
||||
p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
|
||||
|
||||
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
|
||||
|
|
@ -53,7 +52,7 @@ class _CRG(Module):
|
|||
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.sata_reset),
|
||||
]
|
||||
|
||||
class UART2WB(Module):
|
||||
class GenSoC(Module):
|
||||
csr_base = 0x00000000
|
||||
csr_data_width = 8
|
||||
csr_map = {
|
||||
|
|
@ -63,6 +62,7 @@ class UART2WB(Module):
|
|||
interrupt_map = {}
|
||||
cpu_type = None
|
||||
def __init__(self, platform, clk_freq):
|
||||
# UART <--> Wishbone bridge
|
||||
self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)
|
||||
|
||||
# CSR bridge 0x00000000 (shadow @0x00000000)
|
||||
|
|
@ -71,20 +71,9 @@ class UART2WB(Module):
|
|||
self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
|
||||
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
|
||||
|
||||
|
||||
# CSR
|
||||
self.identifier = identifier.Identifier(0, int(clk_freq), 0)
|
||||
|
||||
def add_wb_master(self, wbm):
|
||||
if self.finalized:
|
||||
raise FinalizeError
|
||||
self._wb_masters.append(wbm)
|
||||
|
||||
def add_wb_slave(self, address_decoder, interface):
|
||||
if self.finalized:
|
||||
raise FinalizeError
|
||||
self._wb_slaves.append((address_decoder, interface))
|
||||
|
||||
def add_cpu_memory_region(self, name, origin, length):
|
||||
self.cpu_memory_regions.append((name, origin, length))
|
||||
|
||||
|
|
@ -106,40 +95,26 @@ class UART2WB(Module):
|
|||
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
|
||||
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
|
||||
|
||||
class SimDesign(UART2WB):
|
||||
default_platform = "kc705"
|
||||
|
||||
def __init__(self, platform, export_mila=False):
|
||||
clk_freq = 166*1000000
|
||||
UART2WB.__init__(self, platform, clk_freq)
|
||||
self.crg = _CRG(platform)
|
||||
|
||||
sata_phy_host = SATAPHY(platform.request("sata_host"), clk_freq, host=True)
|
||||
self.comb += [
|
||||
self.sata_phy_host.sink.stb.eq(1),
|
||||
self.sata_phy_host.sink.data.eq(primitives["SYNC"]),
|
||||
self.sata_phy_host.sink.charisk.eq(0b0001)
|
||||
]
|
||||
self.sata_phy_device = SATAPHY(platform.request("sata_device"), clk_freq, host=False)
|
||||
self.comb += [
|
||||
self.sata_phy_device.sink.stb.eq(1),
|
||||
self.sata_phy_device.sink.data.eq(primitives["SYNC"]),
|
||||
self.sata_phy_device.sink.charisk.eq(0b0001)
|
||||
]
|
||||
|
||||
class DebugLeds(Module):
|
||||
class BISTLeds(Module):
|
||||
def __init__(self, platform, sata_phy):
|
||||
# blinking leds (sata_rx and sata_tx clocks)
|
||||
# 1Hz blinking leds (sata_rx and sata_tx clocks)
|
||||
sata_rx_led = platform.request("user_led", 0)
|
||||
sata_tx_led = platform.request("user_led", 1)
|
||||
|
||||
sata_rx_cnt = Signal(32)
|
||||
sata_tx_cnt = Signal(32)
|
||||
|
||||
sata_freqs_mhz = {
|
||||
"SATA3" : 150.0,
|
||||
"SATA2" : 75.0,
|
||||
"SATA1" : 37.5,
|
||||
}
|
||||
sata_freq = int(sata_freqs_mhz[sata_phy.speed]*1000*1000)
|
||||
|
||||
self.sync.sata_rx += \
|
||||
If(sata_rx_cnt == 0,
|
||||
sata_rx_led.eq(~sata_rx_led),
|
||||
sata_rx_cnt.eq(150*1000*1000//2)
|
||||
sata_rx_cnt.eq(sata_freq//2)
|
||||
).Else(
|
||||
sata_rx_cnt.eq(sata_rx_cnt-1)
|
||||
)
|
||||
|
|
@ -147,7 +122,7 @@ class DebugLeds(Module):
|
|||
self.sync.sata_tx += \
|
||||
If(sata_tx_cnt == 0,
|
||||
sata_tx_led.eq(~sata_tx_led),
|
||||
sata_tx_cnt.eq(150*1000*1000//2)
|
||||
sata_tx_cnt.eq(sata_freq//2)
|
||||
).Else(
|
||||
sata_tx_cnt.eq(sata_tx_cnt-1)
|
||||
)
|
||||
|
|
@ -156,62 +131,71 @@ class DebugLeds(Module):
|
|||
self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready)
|
||||
self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready)
|
||||
|
||||
class TestDesign(UART2WB, AutoCSR):
|
||||
class BISTSoC(GenSoC, AutoCSR):
|
||||
default_platform = "kc705"
|
||||
csr_map = {
|
||||
"sata_bist": 10,
|
||||
"mila": 11
|
||||
}
|
||||
csr_map.update(UART2WB.csr_map)
|
||||
csr_map.update(GenSoC.csr_map)
|
||||
|
||||
def __init__(self, platform, with_mila=False, export_mila=False):
|
||||
def __init__(self, platform, export_mila=False):
|
||||
clk_freq = 166*1000000
|
||||
UART2WB.__init__(self, platform, clk_freq)
|
||||
GenSoC.__init__(self, platform, clk_freq)
|
||||
self.crg = _CRG(platform)
|
||||
|
||||
# SATA PHY and controller
|
||||
self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA2")
|
||||
self.comb += self.crg.sata_reset.eq(self.sata_phy.ctrl.need_reset)
|
||||
self.sata_con = SATACON(self.sata_phy)
|
||||
|
||||
# SATA BIST generator and checker
|
||||
self.sata_bist = SATABIST(self.sata_con.crossbar.get_ports(2), with_control=True)
|
||||
|
||||
self.leds = DebugLeds(platform, self.sata_phy)
|
||||
# Status Leds
|
||||
self.leds = BISTLeds(platform, self.sata_phy)
|
||||
|
||||
if with_mila:
|
||||
debug = (
|
||||
self.sata_phy.ctrl.ready,
|
||||
class BISTSoCDevel(BISTSoC, AutoCSR):
|
||||
csr_map = {
|
||||
"mila": 11
|
||||
}
|
||||
csr_map.update(BISTSoC.csr_map)
|
||||
def __init__(self, platform, export_mila=False):
|
||||
BISTSoC.__init__(self, platform, export_mila)
|
||||
|
||||
self.sata_phy.source.stb,
|
||||
self.sata_phy.source.data,
|
||||
self.sata_phy.source.charisk,
|
||||
debug = (
|
||||
self.sata_phy.ctrl.ready,
|
||||
|
||||
self.sata_phy.sink.stb,
|
||||
self.sata_phy.sink.data,
|
||||
self.sata_phy.sink.charisk,
|
||||
self.sata_phy.source.stb,
|
||||
self.sata_phy.source.data,
|
||||
self.sata_phy.source.charisk,
|
||||
|
||||
self.sata_con.command.sink.stb,
|
||||
self.sata_con.command.sink.sop,
|
||||
self.sata_con.command.sink.eop,
|
||||
self.sata_con.command.sink.ack,
|
||||
self.sata_con.command.sink.write,
|
||||
self.sata_con.command.sink.read,
|
||||
self.sata_phy.sink.stb,
|
||||
self.sata_phy.sink.data,
|
||||
self.sata_phy.sink.charisk,
|
||||
|
||||
self.sata_con.command.source.stb,
|
||||
self.sata_con.command.source.sop,
|
||||
self.sata_con.command.source.eop,
|
||||
self.sata_con.command.source.ack,
|
||||
self.sata_con.command.source.write,
|
||||
self.sata_con.command.source.read,
|
||||
self.sata_con.command.source.success,
|
||||
self.sata_con.command.source.failed,
|
||||
self.sata_con.command.source.data
|
||||
)
|
||||
self.sata_con.command.sink.stb,
|
||||
self.sata_con.command.sink.sop,
|
||||
self.sata_con.command.sink.eop,
|
||||
self.sata_con.command.sink.ack,
|
||||
self.sata_con.command.sink.write,
|
||||
self.sata_con.command.sink.read,
|
||||
|
||||
self.mila = MiLa(depth=2048, dat=Cat(*debug))
|
||||
self.mila.add_port(Term)
|
||||
if export_mila:
|
||||
mila_filename = os.path.join(platform.soc_ext_path, "test", "mila.csv")
|
||||
self.mila.export(self, debug, mila_filename)
|
||||
self.sata_con.command.source.stb,
|
||||
self.sata_con.command.source.sop,
|
||||
self.sata_con.command.source.eop,
|
||||
self.sata_con.command.source.ack,
|
||||
self.sata_con.command.source.write,
|
||||
self.sata_con.command.source.read,
|
||||
self.sata_con.command.source.success,
|
||||
self.sata_con.command.source.failed,
|
||||
self.sata_con.command.source.data
|
||||
)
|
||||
|
||||
#default_subtarget = SimDesign
|
||||
default_subtarget = TestDesign
|
||||
self.mila = MiLa(depth=2048, dat=Cat(*debug))
|
||||
self.mila.add_port(Term)
|
||||
if export_mila:
|
||||
mila_filename = os.path.join(platform.soc_ext_path, "test", "mila.csv")
|
||||
self.mila.export(self, debug, mila_filename)
|
||||
|
||||
#default_subtarget = BISTSoC
|
||||
default_subtarget = BISTSoCDevel
|
||||
Loading…
Reference in New Issue