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Build your hardware, easily!
165 Commits 40 Branches 14 Tags 51 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
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Florent Kermarrec 083bd54121 global clean up 
- remove initial sims
- remove SATAPHYDeviceCtrl
- rename to LiteSATA
- rename test to bist
 		2015-01-16 20:26:15 +01:00
lib/sata global clean up 2015-01-16 20:26:15 +01:00
platforms add need_reset from controller to request system reset when SATA is not locked 2015-01-15 00:56:47 +01:00
targets global clean up 2015-01-16 20:26:15 +01:00
test bist: use hardware counter for speed calc and remove loops mode 2015-01-16 18:48:34 +01:00
Makefile global clean up 2015-01-16 20:26:15 +01:00
README global clean up 2015-01-16 20:26:15 +01:00

README 

--------------------------------------------------------------------------------
                      __   _ __      _______ _________
                     / /  (_) /____ / __/ _ /_  __/ _ |
                    / /__/ / __/ -_)\ \/ __ |/ / / __ |
                   /____/_/\__/\__/___/_/ |_/_/ /_/ |_|

        Copyright 2014-2015 / Florent Kermarrec / florent@enjoy-digital.fr

                A lite open-source SATA1/2/3 controller
	     developed in partnership with M-Labs Ltd / HKU
--------------------------------------------------------------------------------

[> Getting started
------------------
1. Install Python3 and Xilinx's Vivado software.

2. Obtain Migen and install it:
  git clone https://github.com/enjoy-digital/migen
  cd migen
  python3 setup.py install
  cd ..

3. Obtain Miscope and install it:
  git clone https://github.com/enjoy-digital/miscope
  cd miscope
  python3 setup.py install
  cd ..

4. Obtain MiSoC:
  git clone https://github.com/enjoy-digital/misoc --recursive

5. Copy lite-sata in working directory and move to it.

6. Build and load design:
  make all

7. Test design:
  go to test directory
  python3 bist.py

[> Simulations :
  Simulation are avalaible in ./lib/sata/test:
    - crc_tb
    - scrambler_tb
    - phy_datapath_tb
    - link_tb
    - command_tb
    - bist_tb
  hdd.py is a HDD model with implementing all SATA layers.
  To run a simulation, move to the simulation directory and run:
    make simulation_name

[> Tests :
  A synthetisable BIST is provided. It can be controled with ./test/bist.py

[> Contact
E-mail: florent@enjoy-digital.fr