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integration/soc/add_uart: add Model/Sim.

This commit is contained in:
Florent Kermarrec 2020-03-25 18:56:58 +01:00
parent 3f43c6a223
commit 09a3ce0ee5
1 changed files with 7 additions and 0 deletions
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7
litex/soc/integration/soc.py
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@ -931,6 +931,13 @@ class LiteXSoC(SoC):
elif name in ["crossover"]:
self.submodules.uart = uart.UARTCrossover()
# Model/Sim
elif name in ["model", "sim"]:
self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth))
# JTAG Atlantic
elif name in ["jtag_atlantic"]:
from litex.soc.cores.jtag import JTAGAtlantic