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bios/sdram: use same initialization procedure for artix7 than kintex7 excepting write leveling that is not done

This commit is contained in:
Florent Kermarrec 2017-12-29 17:13:58 +01:00
parent b78a4760bb
commit 0a2d38ecd2
3 changed files with 19 additions and 32 deletions
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2
litex/boards/targets/arty.py
View File

@ -108,8 +108,6 @@ class BaseSoC(SoCSDRAM):
# sdram # sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 3)
self.add_constant("A7DDRPHY_DELAY", 14)
sdram_module = MT41K128M16(self.clk_freq, "1:4") sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.geom_settings,

2
litex/soc/software/bios/main.c
View File

@ -384,7 +384,7 @@ static void do_command(char *c)
else if(strcmp(token, "sdrrderr") == 0) sdrrderr(get_token(&c)); else if(strcmp(token, "sdrrderr") == 0) sdrrderr(get_token(&c));
else if(strcmp(token, "sdrwr") == 0) sdrwr(get_token(&c)); else if(strcmp(token, "sdrwr") == 0) sdrwr(get_token(&c));
#ifdef CSR_DDRPHY_BASE #ifdef CSR_DDRPHY_BASE
#ifndef A7DDRPHY_BITSLIP #ifdef CSR_DDRPHY_WLEVEL_EN_ADDR
else if(strcmp(token, "sdrwlon") == 0) sdrwlon(); else if(strcmp(token, "sdrwlon") == 0) sdrwlon();
else if(strcmp(token, "sdrwloff") == 0) sdrwloff(); else if(strcmp(token, "sdrwloff") == 0) sdrwloff();
#endif #endif

47
litex/soc/software/bios/sdram.c
View File

@ -195,7 +195,14 @@ void sdrwr(char *startaddr)
} }
#ifdef CSR_DDRPHY_BASE #ifdef CSR_DDRPHY_BASE
#ifndef A7DDRPHY_BITSLIP
#ifdef KUSDDRPHY
#define ERR_DDRPHY_DELAY 512
#else
#define ERR_DDRPHY_DELAY 32
#endif
#ifdef CSR_DDRPHY_WLEVEL_EN_ADDR
void sdrwlon(void) void sdrwlon(void)
{ {
@ -213,12 +220,6 @@ void sdrwloff(void)
ddrphy_wlevel_en_write(0); ddrphy_wlevel_en_write(0);
} }
#ifdef KUSDDRPHY
#define ERR_DDRPHY_DELAY 512
#else
#define ERR_DDRPHY_DELAY 32
#endif
static int write_level(int *delay, int *high_skew) static int write_level(int *delay, int *high_skew)
{ {
int i; int i;
@ -289,6 +290,8 @@ static int write_level(int *delay, int *high_skew)
return ok; return ok;
} }
#endif /* CSR_DDRPHY_WLEVEL_EN_ADDR */
static void read_bitslip(int *delay, int *high_skew) static void read_bitslip(int *delay, int *high_skew)
{ {
int bitslip_thr; int bitslip_thr;
@ -425,7 +428,6 @@ static void read_delays(void)
printf("completed\n"); printf("completed\n");
} }
#endif /* A7DDRPHY_BITSLIP */
#endif /* CSR_DDRPHY_BASE */ #endif /* CSR_DDRPHY_BASE */
static unsigned int seed_to_data_32(unsigned int seed, int random) static unsigned int seed_to_data_32(unsigned int seed, int random)
@ -596,40 +598,27 @@ int memtest(void)
} }
#ifdef CSR_DDRPHY_BASE #ifdef CSR_DDRPHY_BASE
#ifdef A7DDRPHY_BITSLIP
int sdrlevel(void)
{
int bitslip, delay, module;
int i;
sdram_dfii_control_write(DFII_CONTROL_SEL);
for(module=0; module<8; module++) {
ddrphy_dly_sel_write(1<<module);
ddrphy_rdly_dq_rst_write(1);
for(bitslip=0; bitslip<A7DDRPHY_BITSLIP; bitslip++) {
// 7-series SERDES in DDR mode needs 3 pulses for 1 bitslip
for(i=0; i<3; i++)
ddrphy_rdly_dq_bitslip_write(1);
}
for(delay=0; delay<A7DDRPHY_DELAY; delay++)
ddrphy_rdly_dq_inc_write(1);
}
return 1;
}
#else
int sdrlevel(void) int sdrlevel(void)
{ {
int delay[DFII_PIX_DATA_SIZE/2]; int delay[DFII_PIX_DATA_SIZE/2];
int high_skew[DFII_PIX_DATA_SIZE/2]; int high_skew[DFII_PIX_DATA_SIZE/2];
#ifndef CSR_DDRPHY_WLEVEL_EN_ADDR
int i;
for(i=0; i<DFII_PIX_DATA_SIZE/2; i++) {
delay[i] = 0;
high_skew[i] = 0;
}
#else
if(!write_level(delay, high_skew)) if(!write_level(delay, high_skew))
return 0; return 0;
#endif
read_bitslip(delay, high_skew); read_bitslip(delay, high_skew);
read_delays(); read_delays();
return 1; return 1;
} }
#endif #endif
#endif
int sdrinit(void) int sdrinit(void)
{ {