cpu/vexriscv_smp: Use specific Ram_1w_1rs implementation on Efinix FPGAs.

litex/build/efinix/__init__.py

@@ -1,3 +1,4 @@
 from litex.build.efinix.programmer import EfinixProgrammer
 from litex.build.efinix.dbparser import EfinixDbParser
-from litex.build.efinix.ifacewriter import InterfaceWriter
+from litex.build.efinix.ifacewriter import InterfaceWriter
+from litex.build.efinix.platform import EfinixPlatform

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -364,6 +364,10 @@ class VexRiscvSMP(CPU):
         from litex.build.altera import AlteraPlatform
         if isinstance(platform, AlteraPlatform):
             ram_filename = "Ram_1w_1rs_Intel.v"
+        # On Efinix platforms, use specific implementation.
+        from litex.build.efinix import EfinixPlatform
+        if isinstance(platform, EfinixPlatform):
+            ram_filename = "Ram_1w_1rs_Efinix.v"
         platform.add_source(os.path.join(vdir, ram_filename), "verilog")
 
         # Add Cluster.