soc/interconnect/stream: add support for buffered async fifo
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@ -106,8 +106,11 @@ class SyncFIFO(_FIFOWrapper):
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class AsyncFIFO(_FIFOWrapper):
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def __init__(self, layout, depth):
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_FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth)
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def __init__(self, layout, depth, buffered=False):
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_FIFOWrapper.__init__(
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self,
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fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
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layout, depth)
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class Multiplexer(Module):
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