Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fhdl: make WRITE_FIRST default

This commit is contained in:
Sebastien Bourdeauducq 2012-01-27 21:35:58 +01:00
parent 2726ba2242
commit 0cc7e2ac1e
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/migen.txt
View File

@ -310,7 +310,7 @@ Each port description contains:
in each sub-word. If it is set to 0, the port is using whole-word
writes only and the width of the write enable signal must be 1. This
parameter is ignored if there is no write enable signal.
- the mode of the port (default READ_FIRST, ignored for asynchronous
- the mode of the port (default WRITE_FIRST, ignored for asynchronous
ports). It can be:
* READ_FIRST: during a write, the previous value is read.
* WRITE_FIRST: the written value is returned.

2
migen/fhdl/structure.py
View File

@ -232,7 +232,7 @@ class Instance:
class MemoryPort:
def __init__(self, adr, dat_r, we=None, dat_w=None,
async_read=False, re=None, we_granularity=0, mode=READ_FIRST):
async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST):
self.adr = adr
self.dat_r = dat_r
self.we = we