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gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal)

This commit is contained in:
Florent Kermarrec 2017-04-25 10:56:19 +02:00
parent 456cce3ec6
commit 0daeff8689
1 changed files with 5 additions and 5 deletions
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10
litex/gen/sim/core.py
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@ -41,7 +41,7 @@ class TimeManager:
else:
high = False
self.clocks[k] = ClockState(high, half_period, half_period - phase)
def tick(self):
rising = set()
falling = set()
@ -64,14 +64,14 @@ str2op = {
"+": operator.add,
"-": operator.sub,
"*": operator.mul,
">>>": operator.rshift,
"<<<": operator.lshift,
"&": operator.and_,
"^": operator.xor,
"|": operator.or_,
"<": operator.lt,
"<=": operator.le,
"==": operator.eq,
@ -271,7 +271,7 @@ class Simulator:
self.time = TimeManager(clocks)
for clock in clocks.keys():
if clock not in self.fragment.clock_domains:
cd = ClockDomain(name=clock, reset_less=True)
cd = ClockDomain(name=clock)
cd.clk.reset = C(self.time.clocks[clock].high)
self.fragment.clock_domains.append(cd)