litesata: move file and modify import to misoclib.mem.litesata

misoclib/mem/.gitignore

@@ -1,3 +0,0 @@
-__pycache__
-*.pyc
-*.vcd

misoclib/mem/litesata/__init__.py

@@ -1,7 +1,7 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.phy import *
+from misoclib.mem.litesata.phy import *
-from litesata.core import *
+from misoclib.mem.litesata.core import *
-from litesata.frontend import *
+from misoclib.mem.litesata.frontend import *
 
 from migen.bank.description import *
 

misoclib/mem/litesata/core/__init__.py

@@ -1,7 +1,7 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link import LiteSATALink
+from misoclib.mem.litesata.core.link import LiteSATALink
-from litesata.core.transport import LiteSATATransport
+from misoclib.mem.litesata.core.transport import LiteSATATransport
-from litesata.core.command import LiteSATACommand
+from misoclib.mem.litesata.core.command import LiteSATACommand
 
 class LiteSATACore(Module):
 	def __init__(self, phy, buffer_depth):

misoclib/mem/litesata/core/command/__init__.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 tx_to_rx = [
 	("write", 1),

misoclib/mem/litesata/core/link/__init__.py

@@ -1,7 +1,7 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link.crc import LiteSATACRCInserter, LiteSATACRCChecker
+from misoclib.mem.litesata.core.link.crc import LiteSATACRCInserter, LiteSATACRCChecker
-from litesata.core.link.scrambler import LiteSATAScrambler
+from misoclib.mem.litesata.core.link.scrambler import LiteSATAScrambler
-from litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
+from misoclib.mem.litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
 
 from_rx = [
 	("idle", 1),

misoclib/mem/litesata/core/link/cont.py

@@ -1,5 +1,5 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link.scrambler import Scrambler
+from misoclib.mem.litesata.core.link.scrambler import Scrambler
 
 class LiteSATACONTInserter(Module):
 	def __init__(self, description):

misoclib/mem/litesata/core/link/crc.py

@@ -1,5 +1,5 @@
 from collections import OrderedDict
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 from migen.actorlib.crc import CRCInserter, CRCChecker
 

misoclib/mem/litesata/core/link/scrambler.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 @DecorateModule(InsertCE)
 class Scrambler(Module):

misoclib/mem/litesata/core/transport/__init__.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 def _get_item(obj, name, width):
 	if "_lsb" in name:

misoclib/mem/litesata/example_designs/make.py

@@ -8,9 +8,10 @@ from migen.fhdl import verilog, edif
 from migen.fhdl.structure import _Fragment
 from migen.bank.description import CSRStatus
 from mibuild import tools
-from mibuild.xilinx_common import *
+from mibuild.xilinx.common import *
 
-from litesata.common import *
+sys.path.append("../../../../") # Temporary
+from misoclib.mem.litesata.common import *
 
 def get_csr_csv(regions):
 	r = ""

misoclib/mem/litesata/example_designs/targets/bist.py

@@ -1,6 +1,6 @@
 import os
 
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 from migen.bank import csrgen
 from migen.bus import wishbone, csr
 from migen.bus import wishbone2csr
@@ -15,9 +15,9 @@ from litescope.bridge.uart2wb import LiteScopeUART2WB
 from litescope.frontend.la import LiteScopeLA
 from litescope.core.port import LiteScopeTerm
 
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.phy import LiteSATAPHY
+from misoclib.mem.litesata.phy import LiteSATAPHY
-from litesata import LiteSATA
+from misoclib.mem.litesata import LiteSATA
 
 class _CRG(Module):
 	def __init__(self, platform):

misoclib/mem/litesata/example_designs/targets/core.py

@@ -2,9 +2,9 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from targets import *
 
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.phy import LiteSATAPHY
+from misoclib.mem.litesata.phy import LiteSATAPHY
-from litesata import LiteSATA
+from misoclib.mem.litesata import LiteSATA
 
 class LiteSATACore(Module):
 	default_platform = "verilog_backend"

misoclib/mem/litesata/frontend/__init__.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.frontend.crossbar import LiteSATACrossbar
+from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
-from litesata.frontend.arbiter import LiteSATAArbiter
+from misoclib.mem.litesata.frontend.arbiter import LiteSATAArbiter
-from litesata.frontend.bist import LiteSATABIST
+from misoclib.mem.litesata.frontend.bist import LiteSATABIST

misoclib/mem/litesata/frontend/arbiter.py

@@ -1,5 +1,5 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.frontend.common import *
+from misoclib.mem.litesata.frontend.common import *
 
 from migen.genlib.roundrobin import *
 

misoclib/mem/litesata/frontend/bist.py

@@ -1,5 +1,5 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link.scrambler import Scrambler
+from misoclib.mem.litesata.core.link.scrambler import Scrambler
 
 from migen.fhdl.decorators import ModuleDecorator
 from migen.bank.description import *

misoclib/mem/litesata/frontend/common.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 class LiteSATAMasterPort:
 	def __init__(self, dw):

misoclib/mem/litesata/frontend/crossbar.py

@@ -1,6 +1,6 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.frontend.common import *
+from misoclib.mem.litesata.frontend.common import *
-from litesata.frontend.arbiter import LiteSATAArbiter
+from misoclib.mem.litesata.frontend.arbiter import LiteSATAArbiter
 
 class LiteSATACrossbar(Module):
 	def __init__(self, core):

misoclib/mem/litesata/phy/__init__.py

@@ -1,6 +1,6 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.phy.ctrl import *
+from misoclib.mem.litesata.phy.ctrl import *
-from litesata.phy.datapath import *
+from misoclib.mem.litesata.phy.datapath import *
 
 class LiteSATAPHY(Module):
 	def __init__(self, device, pads, revision, clk_freq):
@@ -8,8 +8,8 @@ class LiteSATAPHY(Module):
 		self.revision = revision
 		# Transceiver / Clocks
 		if device[:3] == "xc7": # Kintex 7
-			from litesata.phy.k7.trx import K7LiteSATAPHYTRX
+			from misoclib.mem.litesata.phy.k7.trx import K7LiteSATAPHYTRX
-			from litesata.phy.k7.crg import K7LiteSATAPHYCRG
+			from misoclib.mem.litesata.phy.k7.crg import K7LiteSATAPHYCRG
 			self.submodules.trx = K7LiteSATAPHYTRX(pads, revision)
 			self.submodules.crg = K7LiteSATAPHYCRG(pads, self.trx, revision, clk_freq)
 		else:

misoclib/mem/litesata/phy/ctrl.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 def us(t, clk_freq):
 	clk_period_us = 1000000/clk_freq

misoclib/mem/litesata/phy/datapath.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 class LiteSATAPHYDatapathRX(Module):
 	def __init__(self):

misoclib/mem/litesata/phy/k7/crg.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 class K7LiteSATAPHYCRG(Module):
 	def __init__(self, pads, gtx, revision, clk_freq):

misoclib/mem/litesata/phy/k7/trx.py

@@ -1,4 +1,4 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 def ones(width):
 	return 2**width-1

misoclib/mem/litesata/test/bist_tb.py

@@ -1,9 +1,9 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata import LiteSATA
+from misoclib.mem.litesata import LiteSATA
-from litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
+from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
 
-from litesata.test.hdd import *
+from misoclib.mem.litesata.test.hdd import *
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
 
 class TB(Module):
 	def __init__(self):

misoclib/mem/litesata/test/command_tb.py

@@ -1,8 +1,8 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core import LiteSATACore
+from misoclib.mem.litesata.core import LiteSATACore
 
-from litesata.test.hdd import *
+from misoclib.mem.litesata.test.hdd import *
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
 
 class CommandTXPacket(list):
 	def __init__(self, write=0, read=0, sector=0, count=0, data=[]):

misoclib/mem/litesata/test/common.py

@@ -2,7 +2,7 @@ import random, copy
 
 from migen.sim.generic import run_simulation
 
-from litesata.common import *
+from misoclib.mem.litesata.common import *
 
 def seed_to_data(seed, random=True):
 	if random:

misoclib/mem/litesata/test/cont_tb.py

@@ -1,7 +1,7 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
+from misoclib.mem.litesata.core.link.cont import LiteSATACONTInserter, LiteSATACONTRemover
 
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
 
 class ContPacket(list):
 	def __init__(self, data=[]):

misoclib/mem/litesata/test/crc_tb.py

@@ -1,9 +1,9 @@
 import subprocess
 
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link.crc import *
+from misoclib.mem.litesata.core.link.crc import *
 
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
 
 class TB(Module):
 	def __init__(self, length, random):

misoclib/mem/litesata/test/hdd.py

@@ -1,8 +1,8 @@
 import subprocess
 import math
 
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
 
 def print_with_prefix(s, prefix=""):
 	if not isinstance(s, str):

misoclib/mem/litesata/test/link_tb.py

@@ -1,8 +1,8 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link import LiteSATALink
+from misoclib.mem.litesata.core.link import LiteSATALink
 
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
-from litesata.test.hdd import *
+from misoclib.mem.litesata.test.hdd import *
 
 class LinkStreamer(PacketStreamer):
 	def __init__(self):

misoclib/mem/litesata/test/phy_datapath_tb.py

@@ -1,7 +1,7 @@
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.phy.datapath import LiteSATAPHYDatapath
+from misoclib.mem.litesata.phy.datapath import LiteSATAPHYDatapath
 
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
 
 class DataPacket(list):
 	def __init__(self, data=[]):

misoclib/mem/litesata/test/scrambler_tb.py

@@ -1,9 +1,9 @@
 import subprocess
 
-from litesata.common import *
+from misoclib.mem.litesata.common import *
-from litesata.core.link.scrambler import *
+from misoclib.mem.litesata.core.link.scrambler import *
 
-from litesata.test.common import *
+from misoclib.mem.litesata.test.common import *
 
 class TB(Module):
 	def __init__(self, length):