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targets: self.pll_sys --> pll_sys

This commit is contained in:
Florent Kermarrec 2018-09-13 05:31:35 +02:00
parent 1468b9f3ba
commit 0e68daebf3
5 changed files with 15 additions and 15 deletions
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6
litex/boards/targets/arty.py
View File

@ -31,7 +31,7 @@ class _CRG(Module):
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys = Signal()
pll_sys4x = Signal()
pll_sys4x_dqs = Signal()
pll_clk200 = Signal()
@ -47,7 +47,7 @@ class _CRG(Module):
# 100 MHz
p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
o_CLKOUT0=pll_sys,
# 400 MHz
p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
@ -65,7 +65,7 @@ class _CRG(Module):
p_CLKOUT4_DIVIDE=32, p_CLKOUT4_PHASE=0.0,
o_CLKOUT4=pll_clk50
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),

6
litex/boards/targets/genesys2.py
View File

@ -32,7 +32,7 @@ class _CRG(Module):
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys = Signal()
pll_sys4x = Signal()
pll_clk200 = Signal()
self.specials += [
@ -46,7 +46,7 @@ class _CRG(Module):
# 125MHz
p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
o_CLKOUT0=pll_sys,
# 500MHz
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
@ -56,7 +56,7 @@ class _CRG(Module):
p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0,
o_CLKOUT2=pll_clk200
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst_n),

6
litex/boards/targets/kc705.py
View File

@ -32,7 +32,7 @@ class _CRG(Module):
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys = Signal()
pll_sys4x = Signal()
pll_clk200 = Signal()
self.specials += [
@ -46,7 +46,7 @@ class _CRG(Module):
# 125MHz
p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
o_CLKOUT0=pll_sys,
# 500MHz
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
@ -56,7 +56,7 @@ class _CRG(Module):
p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0,
o_CLKOUT2=pll_clk200
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),

6
litex/boards/targets/nexys4ddr.py
View File

@ -28,7 +28,7 @@ class _CRG(Module):
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys = Signal()
pll_sys2x = Signal()
pll_sys2x_dqs = Signal()
pll_clk200 = Signal()
@ -43,7 +43,7 @@ class _CRG(Module):
# 100 MHz
p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
o_CLKOUT0=pll_sys,
# 200 MHz
p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0,
@ -57,7 +57,7 @@ class _CRG(Module):
p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
o_CLKOUT3=pll_clk200
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys2x, o_O=self.cd_sys2x.clk),
Instance("BUFG", i_I=pll_sys2x_dqs, o_O=self.cd_sys2x_dqs.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),

6
litex/boards/targets/nexys_video.py
View File

@ -31,7 +31,7 @@ class _CRG(Module):
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys = Signal()
pll_sys4x = Signal()
pll_sys4x_dqs = Signal()
pll_clk200 = Signal()
@ -46,7 +46,7 @@ class _CRG(Module):
# 100 MHz
p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
o_CLKOUT0=pll_sys,
# 400 MHz
p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
@ -60,7 +60,7 @@ class _CRG(Module):
p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
o_CLKOUT3=pll_clk200
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),