Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader).

Browse source 
Defaults parameters can allow the FPGA gateware to behave by itself after initialization while still being configurable by software.
This commit is contained in:
Florent Kermarrec 2021-03-04 11:53:43 +01:00
parent 225a518f7e
commit 0ee92448b9
1 changed files with 19 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

38
litex/soc/cores/dma.py
View file

@ -1,7 +1,7 @@
#
# This file is part of LiteX.
#
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020-2021 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
"""Direct Memory Access (DMA) reader and writer modules."""
@ -74,12 +74,12 @@ class WishboneDMAReader(Module, AutoCSR):
if with_csr:
self.add_csr()
def add_csr(self):
self._base = CSRStorage(64)
self._length = CSRStorage(32)
self._enable = CSRStorage()
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
self._base = CSRStorage(64, reset=default_base)
self._length = CSRStorage(32, reset=default_length)
self._enable = CSRStorage(reset=default_enable)
self._done = CSRStatus()
self._loop = CSRStorage()
self._loop = CSRStorage(reset=default_loop)
self._offset = CSRStatus(32)
# # #
@ -116,9 +116,7 @@ class WishboneDMAReader(Module, AutoCSR):
)
)
)
fsm.act("DONE",
self._done.status.eq(1)
)
fsm.act("DONE", self._done.status.eq(1))
# WishboneDMAWriter --------------------------------------------------------------------------------
@ -157,15 +155,16 @@ class WishboneDMAWriter(Module, AutoCSR):
if with_csr:
self.add_csr()
def add_csr(self):
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
self._sink = self.sink
self.sink = stream.Endpoint([("data", self.bus.data_width)])
self._base = CSRStorage(64)
self._length = CSRStorage(32)
self._enable = CSRStorage()
self._base = CSRStorage(64, reset=default_base)
self._length = CSRStorage(32, reset=default_length)
self._enable = CSRStorage(reset=default_enable)
self._done = CSRStatus()
self._loop = CSRStorage()
self._loop = CSRStorage(reset=default_loop)
self._offset = CSRStatus(32)
# # #
@ -176,6 +175,8 @@ class WishboneDMAWriter(Module, AutoCSR):
self.comb += base.eq(self._base.storage[shift:])
self.comb += length.eq(self._length.storage[shift:])
self.comb += self._offset.status.eq(offset)
fsm = FSM(reset_state="IDLE")
fsm = ResetInserter()(fsm)
self.submodules += fsm
@ -187,12 +188,13 @@ class WishboneDMAWriter(Module, AutoCSR):
)
fsm.act("RUN",
self._sink.valid.eq(self.sink.valid),
self._sink.data.eq(self.sink.data),
self._sink.last.eq(offset == (length - 1)),
self._sink.address.eq(base + offset),
self._sink.data.eq(self.sink.data),
self.sink.ready.eq(self._sink.ready),
If(self.sink.valid & self.sink.ready,
NextValue(offset, offset + 1),
If(offset == (length - 1),
If(self._sink.last,
If(self._loop.storage,
NextValue(offset, 0)
).Else(
@ -201,6 +203,4 @@ class WishboneDMAWriter(Module, AutoCSR):
)
)
)
fsm.act("DONE",
self._done.status.eq(1)
)
fsm.act("DONE", self._done.status.eq(1))