cores/up5ksram: optimize bus.adr decoding

2019-07-22 07:55:47 +02:00 · 2019-07-22 07:55:47 +02:00 · 0eff65bb31
parent bb99c4685a
commit 0eff65bb31
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/up5kspram.py
+++ b/litex/soc/cores/up5kspram.py
@ -47,7 +47,7 @@ class Up5kSPRAM(Module):
                wren = Signal()
                self.comb += [
                    datain.eq(self.bus.dat_w[16*w:16*(w+1)]),
-                    If(self.bus.adr[14:16] == d,
+                    If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
                        wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
                        self.bus.dat_r[16*w:16*(w+1)].eq(dataout)
                    ),