cores/up5ksram: optimize bus.adr decoding
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@ -47,7 +47,7 @@ class Up5kSPRAM(Module):
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wren = Signal()
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self.comb += [
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datain.eq(self.bus.dat_w[16*w:16*(w+1)]),
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If(self.bus.adr[14:16] == d,
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If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
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wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
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self.bus.dat_r[16*w:16*(w+1)].eq(dataout)
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),
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