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cores/up5ksram: optimize bus.adr decoding

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This commit is contained in:
Florent Kermarrec 2019-07-22 07:55:47 +02:00
parent bb99c4685a
commit 0eff65bb31
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/up5kspram.py
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@ -47,7 +47,7 @@ class Up5kSPRAM(Module):
wren = Signal()
self.comb += [
datain.eq(self.bus.dat_w[16*w:16*(w+1)]),
If(self.bus.adr[14:16] == d,
If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
self.bus.dat_r[16*w:16*(w+1)].eq(dataout)
),