cpu/openc906: misc fixes/enhancements related to L1$

Currently L1$ flush code does not work well because of lack of
synchorizing.

Switch to use T-Head extended instructions instead of CSRs to flush L1
cache (both D and I), and THEADISAEE is set for this.

In addition, Some other performance-related options are enabled too,
including branch predicting, cache prefetching, etc.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng 2022-11-01 16:10:46 +08:00
parent 5240d28817
commit 0f097fd4c7
2 changed files with 10 additions and 6 deletions

View File

@ -56,8 +56,12 @@ crt_init:
la sp, _fstack la sp, _fstack
la t0, trap_entry la t0, trap_entry
csrw mtvec, t0 csrw mtvec, t0
li t0, 0x3 li t0, 0x400000
csrs 0x7c1, t0 // enable L1I+L1D csrs 0x7c0, t0 // enable THEADISAEE
li t0, 0x73
csrs 0x7c1, t0 // enable L1$ (I+D) + Branch Prediction + Return Stack
li t0, 0x504
csrs 0x7c5, t0 // enable L1$ prefetching
data_init: data_init:
la t0, _fdata la t0, _fdata

View File

@ -35,13 +35,13 @@ void busy_wait_us(unsigned int us);
asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
__attribute__((unused)) static void flush_cpu_icache(void) { __attribute__((unused)) static void flush_cpu_icache(void) {
csrc(0x7c2, 0x33); asm volatile (".long 0x0100000b"); /* icache.iall */
csrs(0x7c2, 0x11); asm volatile (".long 0x01a0000b"); /* sync.i */
}; };
__attribute__((unused)) static void flush_cpu_dcache(void) { __attribute__((unused)) static void flush_cpu_dcache(void) {
csrc(0x7c2, 0x33); asm volatile (".long 0x0030000b"); /* dcache.ciall */
csrs(0x7c2, 0x12); asm volatile (".long 0x01a0000b"); /* sync.i */
}; };
#ifdef __cplusplus #ifdef __cplusplus