cpu/openc906: misc fixes/enhancements related to L1$
Currently L1$ flush code does not work well because of lack of synchorizing. Switch to use T-Head extended instructions instead of CSRs to flush L1 cache (both D and I), and THEADISAEE is set for this. In addition, Some other performance-related options are enabled too, including branch predicting, cache prefetching, etc. Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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@ -56,8 +56,12 @@ crt_init:
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la sp, _fstack
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la sp, _fstack
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la t0, trap_entry
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la t0, trap_entry
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csrw mtvec, t0
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csrw mtvec, t0
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li t0, 0x3
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li t0, 0x400000
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csrs 0x7c1, t0 // enable L1I+L1D
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csrs 0x7c0, t0 // enable THEADISAEE
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li t0, 0x73
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csrs 0x7c1, t0 // enable L1$ (I+D) + Branch Prediction + Return Stack
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li t0, 0x504
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csrs 0x7c5, t0 // enable L1$ prefetching
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data_init:
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data_init:
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la t0, _fdata
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la t0, _fdata
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@ -35,13 +35,13 @@ void busy_wait_us(unsigned int us);
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asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
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asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
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__attribute__((unused)) static void flush_cpu_icache(void) {
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__attribute__((unused)) static void flush_cpu_icache(void) {
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csrc(0x7c2, 0x33);
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asm volatile (".long 0x0100000b"); /* icache.iall */
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csrs(0x7c2, 0x11);
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asm volatile (".long 0x01a0000b"); /* sync.i */
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};
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};
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__attribute__((unused)) static void flush_cpu_dcache(void) {
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__attribute__((unused)) static void flush_cpu_dcache(void) {
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csrc(0x7c2, 0x33);
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asm volatile (".long 0x0030000b"); /* dcache.ciall */
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csrs(0x7c2, 0x12);
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asm volatile (".long 0x01a0000b"); /* sync.i */
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};
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};
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#ifdef __cplusplus
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#ifdef __cplusplus
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