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build/xilinx/vivado: Also generate design checkpoint after synthesis and placement. 

This help exploring/constraining complex designs by using Vivado GUI and design checkpoint.
This commit is contained in:
Florent Kermarrec 2023-07-21 19:53:10 +02:00
parent 35cd744adc
commit 0f1fdea893
2 changed files with 3 additions and 0 deletions
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1
CHANGES.md
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@ -47,6 +47,7 @@
- litepcie/frontend/dma : Added optional integrated data-width converter and data_width parameters to simplify integration/user logic.
- soc/add_uartbone/sata/sdcard : Added support for multiple instances in gateware as for the other cores.
- liteeth_gen : Added raw UDP port support.
- build/vivado : Added .dcp generation also after synthesis and placement.
[> Changed
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2
litex/build/xilinx/vivado.py
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@ -298,6 +298,7 @@ class XilinxVivadoToolchain(GenericToolchain):
tcl.append(f"report_timing_summary -file {self._build_name}_timing_synth.rpt")
tcl.append(f"report_utilization -hierarchical -file {self._build_name}_utilization_hierarchical_synth.rpt")
tcl.append(f"report_utilization -file {self._build_name}_utilization_synth.rpt")
tcl.append(f"write_checkpoint -force {self._build_name}_synth.dcp")
# Optimize
tcl.append("\n# Optimize design\n")
@ -323,6 +324,7 @@ class XilinxVivadoToolchain(GenericToolchain):
tcl.append(f"report_io -file {self._build_name}_io.rpt")
tcl.append(f"report_control_sets -verbose -file {self._build_name}_control_sets.rpt")
tcl.append(f"report_clock_utilization -file {self._build_name}_clock_utilization.rpt")
tcl.append(f"write_checkpoint -force {self._build_name}_place.dcp")
# Add pre-routing commands
tcl.append("\n# Add pre-routing commands\n")