cores directory

2015-09-24 09:05:10 +08:00 · 2015-09-24 09:05:10 +08:00 · 0f410e45f1
parent 83509163df
commit 0f410e45f1
88 changed files with 4 additions and 4 deletions
--- a/.gitmodules
+++ b/.gitmodules
@ -1,8 +1,8 @@
-[submodule "misoc/lm32/verilog/submodule"]
-	path = misoc/lm32/verilog/submodule
+[submodule "misoc/cores/lm32/verilog/submodule"]
+	path = misoc/cores/lm32/verilog/submodule
 	url = https://github.com/m-labs/lm32.git
-[submodule "misoc/mor1kx/verilog"]
-	path = misoc/mor1kx/verilog
+[submodule "misoc/cores/mor1kx/verilog"]
+	path = misoc/cores/mor1kx/verilog
 	url = https://github.com/openrisc/mor1kx.git
 [submodule "software/compiler-rt"]
 	path = software/compiler-rt
--- a/misoc/liteethmini/init.py
+++ b/misoc/liteethmini/init.py
--- a/misoc/cores/dvisampler/init.py
+++ b/misoc/cores/dvisampler/init.py
--- a/misoc/cores/dvisampler/analysis.py
+++ b/misoc/cores/dvisampler/analysis.py
--- a/misoc/cores/dvisampler/chansync.py
+++ b/misoc/cores/dvisampler/chansync.py
--- a/misoc/cores/dvisampler/charsync.py
+++ b/misoc/cores/dvisampler/charsync.py
--- a/misoc/cores/dvisampler/clocking.py
+++ b/misoc/cores/dvisampler/clocking.py
--- a/misoc/cores/dvisampler/common.py
+++ b/misoc/cores/dvisampler/common.py
--- a/misoc/cores/dvisampler/core.py
+++ b/misoc/cores/dvisampler/core.py
--- a/misoc/cores/dvisampler/datacapture.py
+++ b/misoc/cores/dvisampler/datacapture.py
--- a/misoc/cores/dvisampler/debug.py
+++ b/misoc/cores/dvisampler/debug.py
--- a/misoc/cores/dvisampler/decoding.py
+++ b/misoc/cores/dvisampler/decoding.py
--- a/misoc/cores/dvisampler/dma.py
+++ b/misoc/cores/dvisampler/dma.py
--- a/misoc/cores/dvisampler/edid.py
+++ b/misoc/cores/dvisampler/edid.py
--- a/misoc/cores/dvisampler/wer.py
+++ b/misoc/cores/dvisampler/wer.py
--- a/misoc/cores/framebuffer/init.py
+++ b/misoc/cores/framebuffer/init.py
--- a/misoc/cores/framebuffer/core.py
+++ b/misoc/cores/framebuffer/core.py
--- a/misoc/cores/framebuffer/dvi.py
+++ b/misoc/cores/framebuffer/dvi.py
--- a/misoc/cores/framebuffer/format.py
+++ b/misoc/cores/framebuffer/format.py
--- a/misoc/cores/framebuffer/phy.py
+++ b/misoc/cores/framebuffer/phy.py
--- a/misoc/cores/gpio.py
+++ b/misoc/cores/gpio.py
--- a/misoc/cores/identifier.py
+++ b/misoc/cores/identifier.py
--- a/misoc/cores/liteethmini/LICENSE
+++ b/misoc/cores/liteethmini/LICENSE
--- a/misoc/cores/liteethmini/README
+++ b/misoc/cores/liteethmini/README
--- a/misoc/liteethmini/mac/frontend/init.py
+++ b/misoc/liteethmini/mac/frontend/init.py
--- a/misoc/cores/liteethmini/common.py
+++ b/misoc/cores/liteethmini/common.py
--- a/misoc/cores/liteethmini/mac/init.py
+++ b/misoc/cores/liteethmini/mac/init.py
--- a/misoc/cores/liteethmini/mac/core/init.py
+++ b/misoc/cores/liteethmini/mac/core/init.py
--- a/misoc/cores/liteethmini/mac/core/crc.py
+++ b/misoc/cores/liteethmini/mac/core/crc.py
--- a/misoc/cores/liteethmini/mac/core/gap.py
+++ b/misoc/cores/liteethmini/mac/core/gap.py
--- a/misoc/cores/liteethmini/mac/core/last_be.py
+++ b/misoc/cores/liteethmini/mac/core/last_be.py
--- a/misoc/cores/liteethmini/mac/core/padding.py
+++ b/misoc/cores/liteethmini/mac/core/padding.py
--- a/misoc/cores/liteethmini/mac/core/preamble.py
+++ b/misoc/cores/liteethmini/mac/core/preamble.py
--- a/misoc/cores/liteethmini/mac/frontend/init.py
+++ b/misoc/cores/liteethmini/mac/frontend/init.py
--- a/misoc/cores/liteethmini/mac/frontend/sram.py
+++ b/misoc/cores/liteethmini/mac/frontend/sram.py
--- a/misoc/cores/liteethmini/mac/frontend/wishbone.py
+++ b/misoc/cores/liteethmini/mac/frontend/wishbone.py
--- a/misoc/cores/liteethmini/phy/init.py
+++ b/misoc/cores/liteethmini/phy/init.py
--- a/misoc/cores/liteethmini/phy/gmii.py
+++ b/misoc/cores/liteethmini/phy/gmii.py
--- a/misoc/cores/liteethmini/phy/gmii_mii.py
+++ b/misoc/cores/liteethmini/phy/gmii_mii.py
--- a/misoc/cores/liteethmini/phy/loopback.py
+++ b/misoc/cores/liteethmini/phy/loopback.py
--- a/misoc/cores/liteethmini/phy/mii.py
+++ b/misoc/cores/liteethmini/phy/mii.py
--- a/misoc/cores/liteethmini/phy/s6rgmii.py
+++ b/misoc/cores/liteethmini/phy/s6rgmii.py
--- a/misoc/cores/liteethmini/phy/sim.py
+++ b/misoc/cores/liteethmini/phy/sim.py
--- a/misoc/cores/lm32/core.py
+++ b/misoc/cores/lm32/core.py
--- a/misoc/cores/lm32/verilog/lm32_config.v
+++ b/misoc/cores/lm32/verilog/lm32_config.v
--- a/misoc/mem/sdram/phy/init.py
+++ b/misoc/mem/sdram/phy/init.py
--- a/misoc/cores/mor1kx/core.py
+++ b/misoc/cores/mor1kx/core.py
--- a/misoc/cores/mxcrg.v
+++ b/misoc/cores/mxcrg.v
--- a/misoc/cores/norflash16.py
+++ b/misoc/cores/norflash16.py
--- a/misoc/cores/sdram/init.py
+++ b/misoc/cores/sdram/init.py
--- a/misoc/cores/sdram/core/init.py
+++ b/misoc/cores/sdram/core/init.py
--- a/misoc/cores/sdram/core/lasmibus.py
+++ b/misoc/cores/sdram/core/lasmibus.py
--- a/misoc/cores/sdram/core/lasmicon/init.py
+++ b/misoc/cores/sdram/core/lasmicon/init.py
--- a/misoc/cores/sdram/core/lasmicon/bankmachine.py
+++ b/misoc/cores/sdram/core/lasmicon/bankmachine.py
--- a/misoc/cores/sdram/core/lasmicon/multiplexer.py
+++ b/misoc/cores/sdram/core/lasmicon/multiplexer.py
--- a/misoc/cores/sdram/core/lasmicon/perf.py
+++ b/misoc/cores/sdram/core/lasmicon/perf.py
--- a/misoc/cores/sdram/core/lasmicon/refresher.py
+++ b/misoc/cores/sdram/core/lasmicon/refresher.py
--- a/misoc/cores/sdram/core/lasmixbar.py
+++ b/misoc/cores/sdram/core/lasmixbar.py
--- a/misoc/cores/sdram/core/minicon/init.py
+++ b/misoc/cores/sdram/core/minicon/init.py
--- a/misoc/cores/sdram/frontend/init.py
+++ b/misoc/cores/sdram/frontend/init.py
--- a/misoc/cores/sdram/frontend/dma_lasmi.py
+++ b/misoc/cores/sdram/frontend/dma_lasmi.py
--- a/misoc/cores/sdram/frontend/memtest.py
+++ b/misoc/cores/sdram/frontend/memtest.py
--- a/misoc/cores/sdram/frontend/wishbone2lasmi.py
+++ b/misoc/cores/sdram/frontend/wishbone2lasmi.py
--- a/misoc/cores/sdram/module.py
+++ b/misoc/cores/sdram/module.py
--- a/misoc/cores/sdram/phy/init.py
+++ b/misoc/cores/sdram/phy/init.py
--- a/misoc/cores/sdram/phy/dfi.py
+++ b/misoc/cores/sdram/phy/dfi.py
--- a/misoc/cores/sdram/phy/dfii.py
+++ b/misoc/cores/sdram/phy/dfii.py
--- a/misoc/cores/sdram/phy/gensdrphy.py
+++ b/misoc/cores/sdram/phy/gensdrphy.py
--- a/misoc/cores/sdram/phy/initsequence.py
+++ b/misoc/cores/sdram/phy/initsequence.py
--- a/misoc/cores/sdram/phy/k7ddrphy.py
+++ b/misoc/cores/sdram/phy/k7ddrphy.py
--- a/misoc/cores/sdram/phy/s6ddrphy.py
+++ b/misoc/cores/sdram/phy/s6ddrphy.py
--- a/misoc/cores/sdram/phy/simphy.py
+++ b/misoc/cores/sdram/phy/simphy.py
--- a/misoc/cores/sdram/test/abstract_transactions_lasmi.py
+++ b/misoc/cores/sdram/test/abstract_transactions_lasmi.py
--- a/misoc/cores/sdram/test/bankmachine_tb.py
+++ b/misoc/cores/sdram/test/bankmachine_tb.py
--- a/misoc/cores/sdram/test/common.py
+++ b/misoc/cores/sdram/test/common.py
--- a/misoc/cores/sdram/test/lasmicon_df_tb.py
+++ b/misoc/cores/sdram/test/lasmicon_df_tb.py
--- a/misoc/cores/sdram/test/lasmicon_tb.py
+++ b/misoc/cores/sdram/test/lasmicon_tb.py
--- a/misoc/cores/sdram/test/lasmicon_wb.py
+++ b/misoc/cores/sdram/test/lasmicon_wb.py
--- a/misoc/cores/sdram/test/minicon_tb.py
+++ b/misoc/cores/sdram/test/minicon_tb.py
--- a/misoc/cores/sdram/test/refresher.py
+++ b/misoc/cores/sdram/test/refresher.py
--- a/misoc/cores/spi/init.py
+++ b/misoc/cores/spi/init.py
--- a/misoc/cores/spi/core.py
+++ b/misoc/cores/spi/core.py
--- a/misoc/cores/spi/test.py
+++ b/misoc/cores/spi/test.py
--- a/misoc/cores/spiflash.py
+++ b/misoc/cores/spiflash.py
--- a/misoc/cores/timer.py
+++ b/misoc/cores/timer.py
--- a/misoc/cores/uart/init.py
+++ b/misoc/cores/uart/init.py
--- a/misoc/cores/uart/core.py
+++ b/misoc/cores/uart/core.py
--- a/misoc/cores/uart/test.py
+++ b/misoc/cores/uart/test.py