liteXXX cores: remove redefinition of get_csr_csv

This commit is contained in:
Florent Kermarrec 2015-02-28 21:45:05 +01:00
parent 5bd1ab7fa1
commit 0fd1b9df8d
3 changed files with 6 additions and 33 deletions

View File

@ -11,18 +11,9 @@ from mibuild import tools
from mibuild.xilinx.common import *
sys.path.append("../../../../") # Temporary
from misoclib.soc import cpuif
from misoclib.com.liteeth.common import *
def get_csr_csv(regions):
r = ""
for name, origin, busword, obj in regions:
if not isinstance(obj, Memory):
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
origin += 4*nr
return r
def _import(default, name):
return importlib.import_module(default + "." + name)
@ -128,7 +119,7 @@ System Clk: {} MHz
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = get_csr_csv(soc.cpu_csr_regions)
csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-bitstream"]:

View File

@ -11,18 +11,9 @@ from mibuild import tools
from mibuild.xilinx.common import *
sys.path.append("../../../../") # Temporary
from misoclib.soc import cpuif
from misoclib.mem.litesata.common import *
def get_csr_csv(regions):
r = ""
for name, origin, busword, obj in regions:
if not isinstance(obj, Memory):
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
origin += 4*nr
return r
def _import(default, name):
return importlib.import_module(default + "." + name)
@ -134,7 +125,7 @@ BIST: {}
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = get_csr_csv(soc.cpu_csr_regions)
csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:

View File

@ -11,18 +11,9 @@ from mibuild import tools
from mibuild.xilinx.common import *
sys.path.append("../../../../") # Temporary
from misoclib.soc import cpuif
from misoclib.tools.litescope.common import *
def get_csr_csv(regions):
r = ""
for name, origin, busword, obj in regions:
if not isinstance(obj, Memory):
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
origin += 4*nr
return r
def _import(default, name):
return importlib.import_module(default + "." + name)
@ -137,7 +128,7 @@ RLE: {}
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = get_csr_csv(soc.cpu_csr_regions)
csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-bitstream"]: