Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

interconnect/axi: Fix AXILiteDownverterWrite/Read base address. 

Downconverter should start on master's addr, not on aligned master's addr.
This commit is contained in:
Florent Kermarrec 2021-03-10 18:24:55 +01:00
parent 9d08c65e8a
commit 10eff37b84
1 changed files with 2 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
litex/soc/interconnect/axi.py
View File

@ -833,24 +833,18 @@ class _AXILiteDownConverterWrite(Module):
dw_from = len(master.w.data) dw_from = len(master.w.data)
dw_to = len(slave.w.data) dw_to = len(slave.w.data)
ratio = dw_from//dw_to ratio = dw_from//dw_to
master_align = log2_int(master.data_width//8)
slave_align = log2_int(slave.data_width//8)
skip = Signal() skip = Signal()
counter = Signal(max=ratio) counter = Signal(max=ratio)
aw_ready = Signal() aw_ready = Signal()
w_ready = Signal() w_ready = Signal()
resp = Signal.like(master.b.resp) resp = Signal.like(master.b.resp)
addr_counter = Signal(master_align)
# # # # # #
# Slave address counter
self.comb += addr_counter[slave_align:].eq(counter)
# Data path # Data path
self.comb += [ self.comb += [
slave.aw.addr.eq(Cat(addr_counter, master.aw.addr[master_align:])), slave.aw.addr.eq(master.aw.addr + counter*(dw_to//8)),
Case(counter, {i: slave.w.data.eq(master.w.data[i*dw_to:]) for i in range(ratio)}), Case(counter, {i: slave.w.data.eq(master.w.data[i*dw_to:]) for i in range(ratio)}),
Case(counter, {i: slave.w.strb.eq(master.w.strb[i*dw_to//8:]) for i in range(ratio)}), Case(counter, {i: slave.w.strb.eq(master.w.strb[i*dw_to//8:]) for i in range(ratio)}),
master.b.resp.eq(resp), master.b.resp.eq(resp),
@ -930,19 +924,13 @@ class _AXILiteDownConverterRead(Module):
dw_from = len(master.r.data) dw_from = len(master.r.data)
dw_to = len(slave.r.data) dw_to = len(slave.r.data)
ratio = dw_from//dw_to ratio = dw_from//dw_to
master_align = log2_int(master.data_width//8)
slave_align = log2_int(slave.data_width//8)
skip = Signal() skip = Signal()
counter = Signal(max=ratio) counter = Signal(max=ratio)
resp = Signal.like(master.r.resp) resp = Signal.like(master.r.resp)
addr_counter = Signal(master_align)
# # # # # #
# Slave address counter
self.comb += addr_counter[slave_align:].eq(counter)
# Data path # Data path
# Shift the data word # Shift the data word
r_data = Signal(dw_from, reset_less=True) r_data = Signal(dw_from, reset_less=True)
@ -950,7 +938,7 @@ class _AXILiteDownConverterRead(Module):
self.comb += master.r.data.eq(Cat(r_data[dw_to:], slave.r.data)) self.comb += master.r.data.eq(Cat(r_data[dw_to:], slave.r.data))
# Connect address, resp # Connect address, resp
self.comb += [ self.comb += [
slave.ar.addr.eq(Cat(addr_counter, master.ar.addr[master_align:])), slave.ar.addr.eq(master.ar.addr + counter*(dw_to//8)),
master.r.resp.eq(resp), master.r.resp.eq(resp),
] ]