do some clean up
This commit is contained in:
Florent Kermarrec
parent
2fb418a373
commit
111f527647
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@ -3,15 +3,8 @@ from migen.bank.description import *
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class MiIo(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.i = Signal(width)
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self.o = Signal(width)
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self._r_i = CSRStatus(width)
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self._r_o = CSRStorage(width)
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self.sync += [
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self._r_i.status.eq(self.i),
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self.o.eq(self._r_o.storage)
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]
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self.i = self._r_i.status
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self.o = self._r_o.storage
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@ -1,6 +1,5 @@
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from migen.fhdl.structure import *
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from migen.bank.description import *
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from migen.genlib.record import *
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from miscope.std import *
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from miscope.trigger import Trigger
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@ -15,26 +14,23 @@ class MiLa(Module, AutoCSR):
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self.sink = Record(dat_layout(width))
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trigger = Trigger(width, ports)
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recorder = Recorder(width, depth)
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self.submodules.trigger = trigger
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self.submodules.recorder = recorder
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sink_d = Record(dat_layout(width))
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self.sync += sink_d.eq(self.sink)
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self.submodules.trigger = trigger = Trigger(width, ports)
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self.submodules.recorder = recorder = Recorder(width, depth)
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self.comb += [
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sink_d.connect(trigger.sink),
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self.sink.connect(trigger.sink),
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trigger.source.connect(recorder.trig_sink)
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]
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recorder_dat_source = self.sink
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if with_rle:
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self.submodules.rle = RunLengthEncoder(width)
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self.comb += sink_d.connect(self.rle.sink)
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recorder_dat_source = self.rle.source
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self.comb += recorder_dat_source.connect(recorder.dat_sink)
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self.submodules.rle = rle = RunLengthEncoder(width)
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self.comb += [
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self.sink.connect(rle.sink),
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rle.source.connect(recorder.dat_sink)
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]
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else:
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self.sink.connect(recorder.dat_sink)
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def get_csv(self, layout, ns):
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r = ""
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@ -14,11 +14,11 @@ class RunLengthEncoder(Module, AutoCSR):
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self.sink = Record(dat_layout(width))
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self.source = Record(dat_layout(width))
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self._r_enable = CSRStorage()
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self._enable = CSRStorage()
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###
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enable = self._r_enable.storage
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enable = self._enable.storage
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sink_d = Record(dat_layout(width))
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self.sync += If(self.sink.stb, sink_d.eq(self.sink))
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@ -65,14 +65,14 @@ class Recorder(Module, AutoCSR):
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self.trig_sink = Record(hit_layout())
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self.dat_sink = Record(dat_layout(width))
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self._r_trigger = CSR()
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self._r_length = CSRStorage(bits_for(depth))
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self._r_offset = CSRStorage(bits_for(depth))
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self._r_done = CSRStatus()
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self._trigger = CSR()
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self._length = CSRStorage(bits_for(depth))
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self._offset = CSRStorage(bits_for(depth))
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self._done = CSRStatus()
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self._r_read_en = CSR()
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self._r_read_empty = CSRStatus()
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self._r_read_dat = CSRStatus(width)
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self._read_en = CSR()
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self._read_empty = CSRStatus()
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self._read_dat = CSRStatus(width)
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###
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@ -84,24 +84,24 @@ class Recorder(Module, AutoCSR):
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self.comb += [
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self._r_read_empty.status.eq(~fifo.readable),
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self._r_read_dat.status.eq(fifo.dout),
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self._read_empty.status.eq(~fifo.readable),
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self._read_dat.status.eq(fifo.dout),
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]
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fsm.act("IDLE",
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If(self._r_trigger.re & self._r_trigger.r,
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If(self._trigger.re & self._trigger.r,
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NextState("PRE_HIT_RECORDING"),
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fifo.reset.eq(1),
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),
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fifo.re.eq(self._r_read_en.re & self._r_read_en.r),
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self._r_done.status.eq(1)
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fifo.re.eq(self._read_en.re & self._read_en.r),
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self._done.status.eq(1)
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)
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fsm.act("PRE_HIT_RECORDING",
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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fifo.re.eq(fifo.level >= self._r_offset.storage),
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fifo.re.eq(fifo.level >= self._offset.storage),
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If(self.trig_sink.stb & self.trig_sink.hit, NextState("POST_HIT_RECORDING"))
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)
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@ -110,5 +110,5 @@ class Recorder(Module, AutoCSR):
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fifo.we.eq(self.dat_sink.stb),
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fifo.din.eq(self.dat_sink.dat),
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If(~fifo.writable | (fifo.level >= self._r_length.storage), NextState("IDLE"))
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If(~fifo.writable | (fifo.level >= self._length.storage), NextState("IDLE"))
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)
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@ -12,13 +12,13 @@ class Term(Module, AutoCSR):
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._r_trig = CSRStorage(width)
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self._r_mask = CSRStorage(width)
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self._trig = CSRStorage(width)
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self._mask = CSRStorage(width)
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###
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trig = self._r_trig.storage
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mask = self._r_mask.storage
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trig = self._trig.storage
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mask = self._mask.storage
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dat = self.sink.dat
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hit = self.source.hit
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@ -34,13 +34,13 @@ class RangeDetector(Module, AutoCSR):
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._r_low = CSRStorage(width)
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self._r_high = CSRStorage(width)
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self._low = CSRStorage(width)
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self._high = CSRStorage(width)
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###
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low = self._r_low.storage
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high = self._r_high.storage
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low = self._low.storage
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high = self._high.storage
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dat = self.sink.dat
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hit = self.source.hit
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@ -56,15 +56,15 @@ class EdgeDetector(Module, AutoCSR):
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self.sink = Record(dat_layout(width))
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self.source = Record(hit_layout())
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self._r_rising_mask = CSRStorage(width)
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self._r_falling_mask = CSRStorage(width)
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self._r_both_mask = CSRStorage(width)
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self._rising_mask = CSRStorage(width)
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self._falling_mask = CSRStorage(width)
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self._both_mask = CSRStorage(width)
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###
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rising_mask = self._r_rising_mask.storage
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falling_mask = self._r_falling_mask.storage
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both_mask = self._r_both_mask.storage
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rising_mask = self._rising_mask.storage
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falling_mask = self._falling_mask.storage
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both_mask = self._both_mask.storage
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dat = self.sink.dat
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dat_d = Signal(width)
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@ -89,9 +89,9 @@ class Sum(Module, AutoCSR):
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self.sinks = [Record(hit_layout()) for p in range(ports)]
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self.source = Record(hit_layout())
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self._r_prog_we = CSRStorage()
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self._r_prog_adr = CSRStorage(ports) #FIXME
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self._r_prog_dat = CSRStorage()
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self._prog_we = CSRStorage()
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self._prog_adr = CSRStorage(ports) #FIXME
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self._prog_dat = CSRStorage()
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mem = Memory(1, 2**ports)
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lut_port = mem.get_port()
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@ -103,9 +103,9 @@ class Sum(Module, AutoCSR):
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# Lut prog
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self.comb += [
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prog_port.we.eq(self._r_prog_we.storage),
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prog_port.adr.eq(self._r_prog_adr.storage),
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prog_port.dat_w.eq(self._r_prog_dat.storage)
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prog_port.we.eq(self._prog_we.storage),
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prog_port.adr.eq(self._prog_adr.storage),
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prog_port.dat_w.eq(self._prog_dat.storage)
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]
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# Lut read
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