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soc/intergration/soc_core: don't delete uart/timer0 interrupts

This commit is contained in:
Florent Kermarrec 2018-05-01 00:46:26 +02:00
parent 39ffa532b0
commit 121eaba722
1 changed files with 4 additions and 4 deletions
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8
litex/soc/integration/soc_core.py
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@ -146,8 +146,8 @@ class SoCCore(Module):
else: else:
self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy) self.submodules.uart = uart.UART(self.uart_phy)
else: #else:
del self.soc_interrupt_map["uart"] # del self.soc_interrupt_map["uart"]
if ident: if ident:
if ident_version: if ident_version:
@ -158,8 +158,8 @@ class SoCCore(Module):
if with_timer: if with_timer:
self.submodules.timer0 = timer.Timer() self.submodules.timer0 = timer.Timer()
else: #else:
del self.soc_interrupt_map["timer0"] # del self.soc_interrupt_map["timer0"]
# Invert the interrupt map. # Invert the interrupt map.
interrupt_rmap = {} interrupt_rmap = {}