update vexii
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60b0273eda
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122e060a5e
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@ -130,7 +130,7 @@ class VexiiRiscv(CPU):
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print(args)
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print(args)
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if args.update_repo != "no":
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if args.update_repo != "no":
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "c330b794" if args.update_repo=="recommended" else None)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "139a1bd6" if args.update_repo=="recommended" else None)
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