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build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints 

MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.
This commit is contained in:
Florent Kermarrec 2019-04-15 16:48:47 +02:00
parent c252972bef
commit 1275e2f150
1 changed files with 7 additions and 7 deletions
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14
litex/build/xilinx/vivado.py
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@ -197,23 +197,23 @@ class XilinxVivadoToolchain:
# The asynchronous input to a MultiReg is a false path
platform.add_platform_command(
"set_false_path -quiet "
"-to [get_nets -filter {{mr_ff == TRUE}}]"
"-to [get_nets -quiet -filter {{mr_ff == TRUE}}]"
)
# The asychronous reset input to the AsyncResetSynchronizer is a false
# path
platform.add_platform_command(
"set_false_path -quiet "
"-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
"-of [get_cells -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
"-to [get_pins -quiet -filter {{REF_PIN_NAME == PRE}} "
"-of [get_cells -quiet -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
)
# clock_period-2ns to resolve metastability on the wire between the
# AsyncResetSynchronizer FFs
platform.add_platform_command(
"set_max_delay 2 -quiet "
"-from [get_pins -filter {{REF_PIN_NAME == Q}} "
"-of [get_cells -filter {{ars_ff1 == TRUE}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -filter {{ars_ff2 == TRUE}}]]"
"-from [get_pins -quiet -filter {{REF_PIN_NAME == Q}} "
"-of [get_cells -quiet -filter {{ars_ff1 == TRUE}}]] "
"-to [get_pins -quiet -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -quiet -filter {{ars_ff2 == TRUE}}]]"
)
def build(self, platform, fragment, build_dir="build", build_name="top",