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move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)

This commit is contained in:
Florent Kermarrec 2015-02-28 11:45:21 +01:00
parent 8564b7eb6a
commit 1366ff5e26
4 changed files with 2 additions and 2 deletions
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0
misoclib/others/__init__.py Normal file
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misoclib/mxcrg/__init__.py → misoclib/others/mxcrg/__init__.py
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misoclib/mxcrg/mxcrg.v → misoclib/others/mxcrg/mxcrg.v
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4
targets/mlabs_video.py
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@ -4,7 +4,7 @@ from fractions import Fraction
from migen.fhdl.std import * from migen.fhdl.std import *
from mibuild.generic_platform import ConstraintError from mibuild.generic_platform import ConstraintError
from misoclib import mxcrg from misoclib.others import mxcrg
from misoclib.mem import sdram from misoclib.mem import sdram
from misoclib.mem.sdram.phy import s6ddrphy from misoclib.mem.sdram.phy import s6ddrphy
from misoclib.mem.flash import norflash16 from misoclib.mem.flash import norflash16
@ -76,7 +76,7 @@ INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE; PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
""") """)
platform.add_source_dir(os.path.join("misoclib", "mxcrg")) platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg"))
class MiniSoC(BaseSoC): class MiniSoC(BaseSoC):
csr_map = { csr_map = {