Get CSR base addresses from include file
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parent
bb798176fc
commit
141269b384
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@ -0,0 +1,10 @@
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import re
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def get_macros(filename):
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f = open(filename, "r")
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r = {}
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for line in f:
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match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
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if match:
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r[match.group(1)] = match.group(2)
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return r
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12
top.py
12
top.py
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@ -6,6 +6,7 @@ from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
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from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon
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from cmacros import get_macros
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from constraints import Constraints
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MHz = 1000000
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@ -56,6 +57,12 @@ def ddrphy_clocking(crg, phy):
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comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
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return Fragment(comb)
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csr_macros = get_macros("common/csrbase.h")
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def csr_offset(name):
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base = int(csr_macros[name + "_BASE"], 0)
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assert((base >= 0xe0000000) and (base <= 0xe0010000))
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return (base - 0xe0000000)//0x800
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def get():
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#
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# ASMI
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@ -68,7 +75,8 @@ def get():
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# DFI
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#
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ddrphy0 = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
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dfii0 = dfii.DFIInjector(1, sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
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dfii0 = dfii.DFIInjector(csr_offset("DFII"),
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sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
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dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
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dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
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@ -103,7 +111,7 @@ def get():
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#
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# CSR
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#
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uart0 = uart.UART(0, clk_freq, baud=115200)
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uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
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uart0.bank.interface,
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dfii0.bank.interface
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