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xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.

This commit is contained in:
Florent Kermarrec 2020-04-22 10:41:50 +02:00
parent 69462e6669
commit 1457c32052
1 changed files with 23 additions and 24 deletions
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47
litex/build/xilinx/common.py
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@ -1,5 +1,5 @@
# This file is Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk> # This file is Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
# This file is Copyright (c) 2014-2018 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2016-2018 Robert Jordens <jordens@gmail.com> # This file is Copyright (c) 2016-2018 Robert Jordens <jordens@gmail.com>
# This file is Copyright (c) 2015 William D. Jones <thor0505@comcast.net> # This file is Copyright (c) 2015 William D. Jones <thor0505@comcast.net>
# License: BSD # License: BSD
@ -127,6 +127,27 @@ class XilinxDifferentialOutput:
def lower(dr): def lower(dr):
return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
# Common SDRTristate -------------------------------------------------------------------------------
class XilinxSDRTristateImpl(Module):
def __init__(self, io, o, oe, i, clk):
_o = Signal()
_oe_n = Signal()
_i = Signal()
self.specials += SDROutput(o, _o)
self.specials += SDROutput(~oe, _oe_n)
self.specials += SDRInput(_i, i)
self.specials += Instance("IOBUF",
io_IO = io,
o_O = _i,
i_I = _o,
i_T = _oe_n,
)
class XilinxSDRTristate:
@staticmethod
def lower(dr):
return XilinxSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
# Common Special Overrides ------------------------------------------------------------------------- # Common Special Overrides -------------------------------------------------------------------------
@ -135,6 +156,7 @@ xilinx_special_overrides = {
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer, AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
DifferentialInput: XilinxDifferentialInput, DifferentialInput: XilinxDifferentialInput,
DifferentialOutput: XilinxDifferentialOutput, DifferentialOutput: XilinxDifferentialOutput,
SDRTristate: XilinxSDRTristate,
} }
# Spartan6 DDROutput ------------------------------------------------------------------------------- # Spartan6 DDROutput -------------------------------------------------------------------------------
@ -201,28 +223,6 @@ class XilinxSDRInputS6:
def lower(dr): def lower(dr):
return XilinxDDRInputImplS6(dr.i, dr.o, Signal(), dr.clk) return XilinxDDRInputImplS6(dr.i, dr.o, Signal(), dr.clk)
# Spartan6 SDRTristate -----------------------------------------------------------------------------
class XilinxSDRTristateImplS6(Module):
def __init__(self, io, o, oe, i, clk):
_o = Signal()
_oe_n = Signal()
_i = Signal()
self.specials += SDROutput(o, _o)
self.specials += SDROutput(~oe, _oe_n)
self.specials += SDRInput(_i, i)
self.specials += Instance("IOBUF",
io_IO = io,
o_O = _i,
i_I = _o,
i_T = _oe_n,
)
class XilinxSDRTristateS6:
@staticmethod
def lower(dr):
return XilinxSDRTristateImplS6(dr.io, dr.o, dr.oe, dr.i, dr.clk)
# Spartan6 Special Overrides ----------------------------------------------------------------------- # Spartan6 Special Overrides -----------------------------------------------------------------------
xilinx_s6_special_overrides = { xilinx_s6_special_overrides = {
@ -230,7 +230,6 @@ xilinx_s6_special_overrides = {
DDRInput: XilinxDDRInputS6, DDRInput: XilinxDDRInputS6,
SDROutput: XilinxSDROutputS6, SDROutput: XilinxSDROutputS6,
SDRInput: XilinxSDRInputS6, SDRInput: XilinxSDRInputS6,
SDRTristate: XilinxSDRTristateS6,
} }
# 7-Series DDROutput ------------------------------------------------------------------------------- # 7-Series DDROutput -------------------------------------------------------------------------------