buid/io/InferedSDRIO/InferedSDRTristate: avoid unnecessary clk_domain/limitation.

Just create a local clk_domain from clk signal.
This commit is contained in:
Florent Kermarrec 2020-07-08 08:33:52 +02:00
parent b54b3b3362
commit 146ead4c4c

View file

@ -43,12 +43,10 @@ class DifferentialOutput(Special):
# SDR Input/Output ---------------------------------------------------------------------------------
class InferedSDRIO(Module):
def __init__(self, i, o, clk, clk_domain):
if clk_domain is None:
raise NotImplementedError("Attempted to use an InferedSDRIO but no clk_domain specified.")
sync = getattr(self.sync, clk_domain)
sync += o.eq(i)
def __init__(self, i, o, clk):
self.clock_domains.cd_sdrio = ClockDomain(reset_less=True)
self.comb += self.cd_sdrio.clk.eq(clk)
self.sync.sdrio += o.eq(i)
class SDRIO(Special):
def __init__(self, i, o, clk=ClockSignal()):
@ -75,15 +73,13 @@ class SDROutput(SDRIO): pass
# SDR Tristate -------------------------------------------------------------------------------------
class InferedSDRTristate(Module):
def __init__(self, io, o, oe, i, clk, clk_domain):
if clk_domain is None:
raise NotImplementedError("Attempted to use an SDRTristate but no clk_domain specified.")
def __init__(self, io, o, oe, i, clk):
_o = Signal()
_oe = Signal()
_i = Signal()
self.specials += SDROutput(o, _o, clk)
self.specials += SDRInput(_i, i, clk)
self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain)
self.submodules += InferedSDRIO(oe, _oe, clk)
self.specials += Tristate(io, _o, _oe, _i)
class SDRTristate(Special):
@ -95,7 +91,6 @@ class SDRTristate(Special):
self.oe = wrap(oe)
self.i = wrap(i)
self.clk = wrap(clk)
self.clk_domain = None if not hasattr(clk, "cd") else clk.cd
def iter_expressions(self):
yield self, "io", SPECIAL_INOUT
@ -106,7 +101,7 @@ class SDRTristate(Special):
@staticmethod
def lower(dr):
return InferedSDRTristate(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.clk_domain)
return InferedSDRTristate(dr.io, dr.o, dr.oe, dr.i, dr.clk)
# DDR Input/Output ---------------------------------------------------------------------------------