Merge pull request #1581 from trabucayre/gowinpll_fix_warnings

soc/cores/clock/gowin_gw1n: fix size for ODSEL, FBDSEL, IDSEL, PSDA, DUTYDA, FDLY

litex/soc/cores/clock/gowin_gw1n.py

@@ -179,12 +179,12 @@ class GW1NPLL(Module):
             i_CLKFB   = 0,              # Clk Feedback.
             i_RESET   = self.reset,     # PLL Reset.
             i_RESET_P = 0,              # PLL Power Down.
-            i_ODSEL   = 0,          # Dynamic ODIV control.
-            i_FBDSEL  = 0,          # Dynamic IDIV control.
-            i_IDSEL   = 0,          # Dynamic FDIV control.
-            i_PSDA    = 0,          # Dynamic phase control.
-            i_DUTYDA  = 0,          # Dynamic duty cycle control.
-            i_FDLY    = 0,          # Dynamic CLKOUTP delay control.
+            i_ODSEL   = Constant(0, 6), # Dynamic ODIV control.
+            i_FBDSEL  = Constant(0, 6), # Dynamic IDIV control.
+            i_IDSEL   = Constant(0, 6), # Dynamic FDIV control.
+            i_PSDA    = Constant(0, 4), # Dynamic phase control.
+            i_DUTYDA  = Constant(0, 4), # Dynamic duty cycle control.
+            i_FDLY    = Constant(0, 4), # Dynamic CLKOUTP delay control.
         )
         if self.device.startswith('GW1NS'):
             instance_name = 'PLLVR'