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cpu/vexriscv_smp/core: Take into account wishbone_force_32b No Direct Memory Bus error.

This commit is contained in:
Florent Kermarrec 2023-01-20 13:36:06 +01:00
parent 73b88c6de1
commit 1610c643f9
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -487,8 +487,8 @@ class VexRiscvSMP(CPU):
# When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus. # When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus.
if len(self.memory_buses) == 0: if len(self.memory_buses) == 0:
if VexRiscvSMP.with_fpu and not VexRiscvSMP.wishbone_memory: if VexRiscvSMP.with_fpu and (not VexRiscvSMP.wishbone_memory and not VexRiscvSMP.wishbone_force_32b):
raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory to your build command.") raise ValueError("No Direct Memory Bus found, please add --with-wishbone-memory or --wishbone-force-32b to your build command.")
else: else:
VexRiscvSMP.wishbone_memory = True VexRiscvSMP.wishbone_memory = True