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soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)

This commit is contained in:
Gwenhael Goavec-Merou 2023-10-30 18:13:46 +01:00
parent 4b9601bdab
commit 16133359d6
1 changed files with 4 additions and 4 deletions
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8
litex/soc/integration/soc.py
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@ -1482,10 +1482,10 @@ class LiteXSoC(SoC):
self.check_if_exists(name)
uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate)
uartbone = uart.UARTBone(
phy = uartbone_phy,
clk_freq = clk_freq,
cd = cd,
addr_width = self.bus.address_width)
phy = uartbone_phy,
clk_freq = clk_freq,
cd = cd,
address_width = self.bus.address_width)
self.add_module(name=f"{name}_phy", module=uartbone_phy)
self.add_module(name=name, module=uartbone)
self.bus.add_master(name=name, master=uartbone.wishbone)