soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)
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@ -1485,7 +1485,7 @@ class LiteXSoC(SoC):
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phy = uartbone_phy,
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phy = uartbone_phy,
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clk_freq = clk_freq,
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clk_freq = clk_freq,
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cd = cd,
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cd = cd,
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addr_width = self.bus.address_width)
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address_width = self.bus.address_width)
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self.add_module(name=f"{name}_phy", module=uartbone_phy)
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self.add_module(name=f"{name}_phy", module=uartbone_phy)
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self.add_module(name=name, module=uartbone)
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self.add_module(name=name, module=uartbone)
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self.bus.add_master(name=name, master=uartbone.wishbone)
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self.bus.add_master(name=name, master=uartbone.wishbone)
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