Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)

Browse source
This commit is contained in:
Gwenhael Goavec-Merou 2023-10-30 18:13:46 +01:00
parent 4b9601bdab
commit 16133359d6
1 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/integration/soc.py
View file

@ -1485,7 +1485,7 @@ class LiteXSoC(SoC):
phy = uartbone_phy,
clk_freq = clk_freq,
cd = cd,
addr_width = self.bus.address_width)
address_width = self.bus.address_width)
self.add_module(name=f"{name}_phy", module=uartbone_phy)
self.add_module(name=name, module=uartbone)
self.bus.add_master(name=name, master=uartbone.wishbone)