soc/integration/soc: fix typo at UARTBone call (addr_width -> address_width)

2023-10-30 18:13:46 +01:00 · 2023-10-30 18:13:46 +01:00 · 16133359d6
parent 4b9601bdab
commit 16133359d6
1 changed files with 4 additions and 4 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1485,7 +1485,7 @@ class LiteXSoC(SoC):
            phy           = uartbone_phy,
            clk_freq      = clk_freq,
            cd            = cd,
-            addr_width = self.bus.address_width)
+            address_width = self.bus.address_width)
        self.add_module(name=f"{name}_phy", module=uartbone_phy)
        self.add_module(name=name,          module=uartbone)
        self.bus.add_master(name=name, master=uartbone.wishbone)