soc/SoC: Add init_ram method from init_rom, allowing initilization of any RAM of the SoC and switch init_rom to it.
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@ -1061,27 +1061,46 @@ class SoC(LiteXModule, SoCCoreCompat):
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if contents != []:
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if contents != []:
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self.add_config(f"{name}_INIT", 1)
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self.add_config(f"{name}_INIT", 1)
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def init_ram(self, name, contents=[], auto_size=False):
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# RAM Parameters.
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ram = getattr(self, name)
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ram_region = self.bus.regions[name]
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ram_type = {
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True : "ROM",
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False : "RAM",
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}["w" not in ram_region.mode]
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# Size Check.
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if ram_region.size < 4*len(contents):
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self.logger.error("Contents Size ({}) {} {} Size ({}).".format(
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colorer(f"0x{4*len(contents):x}"),
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colorer("exceeds", color="red"),
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ram_type,
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colorer(f"0x{ram_region.size:x}"),
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))
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raise SoCError()
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# RAM Initialization.
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self.logger.info("Initializing {} {} with contents (Size: {}).".format(
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ram_type,
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colorer(name),
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colorer(f"0x{4*len(contents):x}")))
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ram.mem.init = contents
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# RAM Auto-Resize (Optional).
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if auto_size and ("w" not in ram_region.mode):
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self.logger.info("Auto-Resizing {} {} from {} to {}.".format(
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ram_type,
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colorer(name),
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colorer(f"0x{ram_region.size:x}"),
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colorer(f"0x{4*len(contents):x}")))
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ram.mem.depth = len(contents)
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def add_rom(self, name, origin, size, contents=[], mode="rx"):
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def add_rom(self, name, origin, size, contents=[], mode="rx"):
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self.add_ram(name, origin, size, contents, mode=mode)
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self.add_ram(name, origin, size, contents, mode=mode)
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def init_rom(self, name, contents=[], auto_size=True):
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def init_rom(self, name, contents=[], auto_size=True):
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self.logger.info("Initializing ROM {} with contents (Size: {}).".format(
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self.init_ram(name, contents, auto_size)
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colorer(name),
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colorer(f"0x{4*len(contents):x}")))
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if self.bus.regions[name].size < 4*len(contents):
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self.logger.error("Contents Size ({}) {} ROM Size ({}).".format(
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colorer(f"0x{4*len(contents):x}"),
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colorer("exceeds", color="red"),
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colorer(f"0x{self.bus.regions[name].size:x}"),
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))
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raise SoCError()
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getattr(self, name).mem.init = contents
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if auto_size and ("w" not in self.bus.regions[name].mode):
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self.logger.info("Auto-Resizing ROM {} from {} to {}.".format(
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colorer(name),
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colorer(f"0x{self.bus.regions[name].size:x}"),
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colorer(f"0x{4*len(contents):x}")))
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getattr(self, name).mem.depth = len(contents)
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def add_csr_bridge(self, name="csr", origin=None, register=False):
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def add_csr_bridge(self, name="csr", origin=None, register=False):
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csr_bridge_cls = {
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csr_bridge_cls = {
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