soc_core: Minor cosmetic changes.
This commit is contained in:
Florent Kermarrec
parent
f181eabebb
commit
9f49b13f8c
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@ -42,7 +42,7 @@ __all__ = [
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# SoCCore ------------------------------------------------------------------------------------------
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class SoCCore(LiteXSoC):
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# Default register/interrupt/memory mappings (can be redefined by user)
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# Default register/interrupt/memory mappings (can be redefined by user).
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csr_map = {}
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interrupt_map = {}
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mem_map = {
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@ -52,7 +52,7 @@ class SoCCore(LiteXSoC):
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}
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def __init__(self, platform, clk_freq,
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# Bus parameters
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# Bus parameters.
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bus_standard = "wishbone",
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bus_data_width = 32,
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bus_address_width = 32,
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@ -60,62 +60,62 @@ class SoCCore(LiteXSoC):
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bus_bursting = False,
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bus_interconnect = "shared",
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# CPU parameters
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# CPU parameters.
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cpu_type = "vexriscv",
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cpu_reset_address = None,
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cpu_variant = None,
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cpu_cfu = None,
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# CFU parameters
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# CFU parameters.
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cfu_filename = None,
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# ROM parameters
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# ROM parameters.
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integrated_rom_size = 0,
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integrated_rom_mode = "rx",
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integrated_rom_init = [],
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# SRAM parameters
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# SRAM parameters.
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integrated_sram_size = 0x2000,
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integrated_sram_init = [],
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# MAIN_RAM parameters
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# MAIN_RAM parameters.
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integrated_main_ram_size = 0,
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integrated_main_ram_init = [],
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# CSR parameters
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# CSR parameters.
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csr_data_width = 32,
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csr_address_width = 14,
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csr_paging = 0x800,
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csr_ordering = "big",
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# Interrupt parameters
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# Interrupt parameters.
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irq_n_irqs = 32,
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# Identifier parameters
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# Identifier parameters.
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ident = "",
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ident_version = False,
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# UART parameters
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# UART parameters.
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with_uart = True,
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uart_name = "serial",
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uart_baudrate = 115200,
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uart_fifo_depth = 16,
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# Timer parameters
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# Timer parameters.
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with_timer = True,
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timer_uptime = False,
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# Controller parameters
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# Controller parameters.
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with_ctrl = True,
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# JTAGBone
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# JTAGBone.
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with_jtagbone = False,
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jtagbone_chain = 1,
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# UARTBone
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# UARTBone.
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with_uartbone = False,
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# Others
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# Others.
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**kwargs):
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# New LiteXSoC class -----------------------------------------------------------------------
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@ -138,7 +138,7 @@ class SoCCore(LiteXSoC):
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irq_reserved_irqs = {},
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)
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# Attributes
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# Attributes.
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self.mem_regions = self.bus.regions
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self.clk_freq = self.sys_clk_freq
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self.mem_map = self.mem_map
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@ -198,28 +198,29 @@ class SoCCore(LiteXSoC):
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# JTAGBone and jtag_uart can't be used at the same time.
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assert not (with_jtagbone and uart_name == "jtag_uart")
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# UARTBone and serial can't be used at the same time.
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assert not (with_uartbone and uart_name == "serial")
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# Modules instances ------------------------------------------------------------------------
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# Add SoCController
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# Add SoCController.
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if with_ctrl:
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self.add_controller("ctrl")
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# Add CPU
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# Add CPU.
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self.add_cpu(
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name = str(cpu_type),
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variant = "standard" if cpu_variant is None else cpu_variant,
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reset_address = None if integrated_rom_size else cpu_reset_address,
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cfu = cpu_cfu)
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# Add User's interrupts
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# Add User's interrupts.
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if self.irq.enabled:
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for name, loc in self.interrupt_map.items():
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self.irq.add(name, loc)
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# Add integrated ROM
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# Add integrated ROM.
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if integrated_rom_size:
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self.add_rom("rom",
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origin = self.cpu.reset_address,
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@ -228,14 +229,14 @@ class SoCCore(LiteXSoC):
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mode = integrated_rom_mode
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)
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# Add integrated SRAM
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# Add integrated SRAM.
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if integrated_sram_size:
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self.add_ram("sram",
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origin = self.mem_map["sram"],
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size = integrated_sram_size,
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)
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# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
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# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available).
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if integrated_main_ram_size:
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self.add_ram("main_ram",
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origin = self.mem_map["main_ram"],
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@ -243,23 +244,23 @@ class SoCCore(LiteXSoC):
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contents = integrated_main_ram_init,
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)
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# Add Identifier
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# Add Identifier.
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if ident != "":
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self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
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# Add UARTBone
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# Add UARTBone.
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if with_uartbone:
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self.add_uartbone(baudrate=uart_baudrate)
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# Add UART
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# Add UART.
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if with_uart:
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self.add_uart(name="uart", uart_name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth)
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# Add JTAGBone
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# Add JTAGBone.
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if with_jtagbone:
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self.add_jtagbone(chain=jtagbone_chain)
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# Add Timer
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# Add Timer.
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if with_timer:
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self.add_timer(name="timer0")
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if timer_uptime:
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@ -328,7 +329,7 @@ class SoCCore(LiteXSoC):
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def soc_core_args(parser):
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soc_group = parser.add_argument_group(title="SoC options")
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# Bus parameters
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# Bus parameters.
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soc_group.add_argument("--bus-standard", default="wishbone", help="Select bus standard: {}.".format(", ".join(SoCBusHandler.supported_standard)))
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soc_group.add_argument("--bus-data-width", default=32, type=auto_int, help="Bus data-width.")
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soc_group.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width.")
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@ -336,53 +337,53 @@ def soc_core_args(parser):
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soc_group.add_argument("--bus-bursting", action="store_true", help="Enable burst cycles on the bus if supported.")
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soc_group.add_argument("--bus-interconnect", default="shared", help="Select bus interconnect: shared (default) or crossbar.")
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# CPU parameters
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# CPU parameters.
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soc_group.add_argument("--cpu-type", default="vexriscv", help="Select CPU: {}.".format(", ".join(iter(cpu.CPUS.keys()))))
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soc_group.add_argument("--cpu-variant", default=None, help="CPU variant.")
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soc_group.add_argument("--cpu-reset-address", default=None, type=auto_int, help="CPU reset address (Boot from Integrated ROM by default).")
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soc_group.add_argument("--cpu-cfu", default=None, help="Optional CPU CFU file/instance to add to the CPU.")
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# Controller parameters
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# Controller parameters.
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soc_group.add_argument("--no-ctrl", action="store_true", help="Disable Controller.")
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# ROM parameters
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# ROM parameters.
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soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).")
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soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).")
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# SRAM parameters
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# SRAM parameters.
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soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.")
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# MAIN_RAM parameters
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# MAIN_RAM parameters.
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soc_group.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM.")
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# CSR parameters
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# CSR parameters.
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soc_group.add_argument("--csr-data-width", default=32 , type=auto_int, help="CSR bus data-width (8 or 32).")
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soc_group.add_argument("--csr-address-width", default=14, type=auto_int, help="CSR bus address-width.")
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soc_group.add_argument("--csr-paging", default=0x800, type=auto_int, help="CSR bus paging.")
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soc_group.add_argument("--csr-ordering", default="big", help="CSR registers ordering (big or little).")
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# Identifier parameters
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# Identifier parameters.
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soc_group.add_argument("--ident", default=None, type=str, help="SoC identifier.")
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soc_group.add_argument("--no-ident-version", action="store_true", help="Disable date/time in SoC identifier.")
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# UART parameters
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# UART parameters.
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soc_group.add_argument("--no-uart", action="store_true", help="Disable UART.")
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soc_group.add_argument("--uart-name", default="serial", type=str, help="UART type/name.")
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soc_group.add_argument("--uart-baudrate", default=115200, type=auto_int, help="UART baudrate.")
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soc_group.add_argument("--uart-fifo-depth", default=16, type=auto_int, help="UART FIFO depth.")
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# UARTBone parameters
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# UARTBone parameters.
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soc_group.add_argument("--with-uartbone", action="store_true", help="Enable UARTbone.")
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# JTAGBone parameters
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# JTAGBone parameters.
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soc_group.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
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soc_group.add_argument("--jtagbone-chain", default=1, type=int, help="Jtagbone chain index.")
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# Timer parameters
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# Timer parameters.
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soc_group.add_argument("--no-timer", action="store_true", help="Disable Timer.")
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soc_group.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer.")
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# L2 Cache
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# L2 Cache.
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soc_group.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size.")
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def soc_core_argdict(args):
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@ -408,7 +409,7 @@ def soc_core_argdict(args):
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r[a] = arg
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return r
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# SoCMini ---------------------------------------------------------------------------------------
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# SoCMini ------------------------------------------------------------------------------------------
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class SoCMini(SoCCore):
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def __init__(self, *args, **kwargs):
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@ -423,7 +424,7 @@ class SoCMini(SoCCore):
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SoCCore.__init__(self, *args, **kwargs)
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# SoCMini arguments -----------------------------------------------------------------------------
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# SoCMini arguments --------------------------------------------------------------------------------
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soc_mini_args = soc_core_args
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soc_mini_argdict = soc_core_argdict
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