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litex/soc/cores/ussysmon.py: dadr address space bump

This commit is contained in:
Vamsi Vytla 2021-03-03 14:38:27 -08:00
parent 922f85e64b
commit 1793efb50b
1 changed files with 3 additions and 3 deletions
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6
litex/soc/cores/ussysmon.py
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@ -46,7 +46,7 @@ class USSYSMON(Module, AutoCSR):
self.dwe = Signal()
self.den = Signal()
self.drdy = Signal()
self.dadr = Signal(7)
self.dadr = Signal(8)
self.di = Signal(16)
self.do = Signal(16)
self.drp_en = Signal()
@ -103,7 +103,7 @@ class USSYSMON(Module, AutoCSR):
self.sync += [
If(self.drdy,
Case(channel, dict(
(k, v.status.eq(self.do >> 6))
(k, v.status.eq((self.do >> 6) & 0x3ff))
for k, v in channels.items()))
)
]
@ -119,7 +119,7 @@ class USSYSMON(Module, AutoCSR):
self.drp_read = CSR()
self.drp_write = CSR()
self.drp_drdy = CSRStatus()
self.drp_adr = CSRStorage(7, reset_less=True)
self.drp_adr = CSRStorage(8, reset_less=True)
self.drp_dat_w = CSRStorage(16, reset_less=True)
self.drp_dat_r = CSRStatus(16)