litex/soc/cores/ussysmon.py: ADC transfer function

2021-03-03 10:50:58 -08:00 · 2021-03-03 10:50:58 -08:00 · 922f85e64b
parent 71f7ce6a57
commit 922f85e64b
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/ussysmon.py
+++ b/litex/soc/cores/ussysmon.py
@ -103,7 +103,7 @@ class USSYSMON(Module, AutoCSR):
        self.sync += [
                If(self.drdy,
                    Case(channel, dict(
-                        (k, v.status.eq(self.do >> 4))
+                        (k, v.status.eq(self.do >> 6))
                    for k, v in channels.items()))
                )
        ]