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integration/soc/add_pcie: Expose more DMA parameters.

This commit is contained in:
Florent Kermarrec 2023-03-27 17:42:10 +02:00
parent 4b72dd047e
commit 181d414911
1 changed files with 9 additions and 4 deletions
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9
litex/soc/integration/soc.py
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@ -1960,8 +1960,11 @@ class LiteXSoC(SoC):
def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32, def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32,
with_dma_buffering = True, dma_buffering_depth=1024, with_dma_buffering = True, dma_buffering_depth=1024,
with_dma_loopback = True, with_dma_loopback = True,
with_dma_synchronizer = False,
with_dma_monitor = False,
with_dma_status = False,
with_msi = True, with_msi = True,
with_synchronizer = False): ):
# Imports # Imports
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA from litepcie.frontend.dma import LitePCIeDMA
@ -2000,7 +2003,9 @@ class LiteXSoC(SoC):
dma = LitePCIeDMA(phy, endpoint, dma = LitePCIeDMA(phy, endpoint,
with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth, with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth,
with_loopback = with_dma_loopback, with_loopback = with_dma_loopback,
with_synchronizer = with_synchronizer, with_synchronizer = with_dma_synchronizer,
with_monitor = with_dma_monitor,
with_status = with_dma_status,
address_width = address_width address_width = address_width
) )
setattr(self, f"{name}_dma{i}", dma) setattr(self, f"{name}_dma{i}", dma)