Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fhdl/namer: support ClockSignal and ResetSignal. Closes #24

This commit is contained in:
Sebastien Bourdeauducq 2015-09-22 14:30:16 +08:00
parent 2c1553fea2
commit 1857ec6c32
2 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
migen/fhdl/namer.py
View File

@ -227,8 +227,17 @@ class Namespace:
self.counts = {k: 1 for k in reserved_keywords} self.counts = {k: 1 for k in reserved_keywords}
self.sigs = {} self.sigs = {}
self.pnd = pnd self.pnd = pnd
self.clock_domains = dict()
def get_name(self, sig): def get_name(self, sig):
if isinstance(sig, ClockSignal):
sig = self.clock_domains[sig.cd].clk
if isinstance(sig, ResetSignal):
sig = self.clock_domains[sig.cd].rst
if sig is None:
raise ValueError("Attempted to obtain name of non-existent "
"reset signal of domain "+sig.cd)
if sig.name_override is not None: if sig.name_override is not None:
sig_name = sig.name_override sig_name = sig.name_override
else: else:

1
migen/fhdl/verilog.py
View File

@ -342,6 +342,7 @@ def convert(f, ios=None, name="top",
ns = build_namespace(list_signals(f) \ ns = build_namespace(list_signals(f) \
| list_special_ios(f, True, True, True) \ | list_special_ios(f, True, True, True) \
| ios, _reserved_keywords) | ios, _reserved_keywords)
ns.clock_domains = f.clock_domains
r.ns = ns r.ns = ns
src = "/* Machine-generated using Migen */\n" src = "/* Machine-generated using Migen */\n"