361 lines
13 KiB
Python
361 lines
13 KiB
Python
from functools import partial
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from operator import itemgetter
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
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from migen.fhdl.tools import *
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from migen.fhdl.bitcontainer import bits_for, flen
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from migen.fhdl.namer import build_namespace
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from migen.fhdl.conv_output import ConvOutput
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_reserved_keywords = {
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"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
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"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
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"defparam", "design", "disable", "edge", "else", "end", "endcase",
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"endconfig", "endfunction", "endgenerate", "endmodule", "endprimitive",
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"endspecify", "endtable", "endtask", "event", "for", "force", "forever",
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"fork", "function", "generate", "genvar", "highz0", "highz1", "if",
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"ifnone", "incdir", "include", "initial", "inout", "input",
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"instance", "integer", "join", "large", "liblist", "library", "localparam",
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"macromodule", "medium", "module", "nand", "negedge", "nmos", "nor",
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"noshowcancelled", "not", "notif0", "notif1", "or", "output", "parameter",
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"pmos", "posedge", "primitive", "pull0", "pull1" "pulldown",
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"pullup", "pulsestyle_onevent", "pulsestyle_ondetect", "remos", "real",
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"realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran",
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"rtranif0", "rtranif1", "scalared", "showcancelled", "signed", "small",
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"specify", "specparam", "strong0", "strong1", "supply0", "supply1",
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"table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
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"tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
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"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor"
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}
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def _printsig(ns, s):
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if s.signed:
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n = "signed "
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else:
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n = ""
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if flen(s) > 1:
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n += "[" + str(flen(s)-1) + ":0] "
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n += ns.get_name(s)
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return n
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def _printconstant(node):
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if node.signed:
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return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value),
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True)
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else:
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return str(node.nbits) + "'d" + str(node.value), False
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def _printexpr(ns, node):
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if isinstance(node, Constant):
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return _printconstant(node)
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elif isinstance(node, Signal):
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return ns.get_name(node), node.signed
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elif isinstance(node, _Operator):
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arity = len(node.operands)
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r1, s1 = _printexpr(ns, node.operands[0])
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if arity == 1:
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if node.op == "-":
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if s1:
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r = node.op + r1
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else:
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r = "-$signed({1'd0, " + r1 + "})"
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s = True
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else:
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r = node.op + r1
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s = s1
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elif arity == 2:
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r2, s2 = _printexpr(ns, node.operands[1])
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if node.op not in ["<<<", ">>>"]:
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if s2 and not s1:
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r1 = "$signed({1'd0, " + r1 + "})"
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if s1 and not s2:
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r2 = "$signed({1'd0, " + r2 + "})"
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r = r1 + " " + node.op + " " + r2
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s = s1 or s2
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elif arity == 3:
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assert node.op == "m"
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r2, s2 = _printexpr(ns, node.operands[1])
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r3, s3 = _printexpr(ns, node.operands[2])
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if s2 and not s3:
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r3 = "$signed({1'd0, " + r3 + "})"
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if s3 and not s2:
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r2 = "$signed({1'd0, " + r2 + "})"
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r = r1 + " ? " + r2 + " : " + r3
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s = s2 or s3
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else:
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raise TypeError
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return "(" + r + ")", s
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elif isinstance(node, _Slice):
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# Verilog does not like us slicing non-array signals...
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if isinstance(node.value, Signal) \
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and flen(node.value) == 1 \
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and node.start == 0 and node.stop == 1:
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return _printexpr(ns, node.value)
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if node.start + 1 == node.stop:
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sr = "[" + str(node.start) + "]"
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else:
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sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
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r, s = _printexpr(ns, node.value)
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return r + sr, s
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elif isinstance(node, Cat):
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l = [_printexpr(ns, v)[0] for v in reversed(node.l)]
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return "{" + ", ".join(l) + "}", False
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elif isinstance(node, Replicate):
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return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
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else:
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raise TypeError("Expression of unrecognized type: '{}'".format(type(node).__name__))
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(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
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def _printnode(ns, at, level, node):
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if node is None:
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return ""
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elif isinstance(node, _Assign):
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if at == _AT_BLOCKING:
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assignment = " = "
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elif at == _AT_NONBLOCKING:
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assignment = " <= "
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elif is_variable(node.l):
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assignment = " = "
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else:
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assignment = " <= "
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return "\t"*level + _printexpr(ns, node.l)[0] + assignment + _printexpr(ns, node.r)[0] + ";\n"
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elif isinstance(node, (list, tuple)):
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return "".join(list(map(partial(_printnode, ns, at, level), node)))
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elif isinstance(node, If):
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r = "\t"*level + "if (" + _printexpr(ns, node.cond)[0] + ") begin\n"
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r += _printnode(ns, at, level + 1, node.t)
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if node.f:
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r += "\t"*level + "end else begin\n"
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r += _printnode(ns, at, level + 1, node.f)
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r += "\t"*level + "end\n"
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return r
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elif isinstance(node, Case):
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if node.cases:
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r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n"
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css = [(k, v) for k, v in node.cases.items() if isinstance(k, Constant)]
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css = sorted(css, key=lambda x: x[0].value)
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for choice, statements in css:
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r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
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r += _printnode(ns, at, level + 2, statements)
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r += "\t"*(level + 1) + "end\n"
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if "default" in node.cases:
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r += "\t"*(level + 1) + "default: begin\n"
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r += _printnode(ns, at, level + 2, node.cases["default"])
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r += "\t"*(level + 1) + "end\n"
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r += "\t"*level + "endcase\n"
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return r
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else:
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return ""
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else:
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raise TypeError("Node of unrecognized type: "+str(type(node)))
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def _list_comb_wires(f):
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r = set()
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groups = group_by_targets(f.comb)
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for g in groups:
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if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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r |= g[0]
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return r
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def _printheader(f, ios, name, ns,
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reg_initialization):
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sigs = list_signals(f) | list_special_ios(f, True, True, True)
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special_outs = list_special_ios(f, False, True, True)
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inouts = list_special_ios(f, False, False, True)
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targets = list_targets(f) | special_outs
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wires = _list_comb_wires(f) | special_outs
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r = "module " + name + "(\n"
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firstp = True
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for sig in sorted(ios, key=lambda x: x.duid):
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if not firstp:
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r += ",\n"
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firstp = False
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if sig in inouts:
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r += "\tinout " + _printsig(ns, sig)
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elif sig in targets:
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if sig in wires:
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r += "\toutput " + _printsig(ns, sig)
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else:
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r += "\toutput reg " + _printsig(ns, sig)
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else:
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r += "\tinput " + _printsig(ns, sig)
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r += "\n);\n\n"
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for sig in sorted(sigs - ios, key=lambda x: x.duid):
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if sig in wires:
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r += "wire " + _printsig(ns, sig) + ";\n"
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else:
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if reg_initialization:
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r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
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else:
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r += "reg " + _printsig(ns, sig) + ";\n"
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r += "\n"
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return r
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def _printcomb(f, ns,
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display_run,
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dummy_signal,
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blocking_assign):
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r = ""
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if f.comb:
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if dummy_signal:
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# Generate a dummy event to get the simulator
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# to run the combinatorial process once at the beginning.
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syn_off = "// synthesis translate_off\n"
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syn_on = "// synthesis translate_on\n"
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dummy_s = Signal(name_override="dummy_s")
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r += syn_off
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r += "reg " + _printsig(ns, dummy_s) + ";\n"
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r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
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r += syn_on
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groups = group_by_targets(f.comb)
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for n, g in enumerate(groups):
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if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
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else:
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if dummy_signal:
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dummy_d = Signal(name_override="dummy_d")
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r += "\n" + syn_off
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r += "reg " + _printsig(ns, dummy_d) + ";\n"
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r += syn_on
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r += "always @(*) begin\n"
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if display_run:
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r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
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if blocking_assign:
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for t in g[0]:
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r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
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r += _printnode(ns, _AT_BLOCKING, 1, g[1])
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else:
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for t in g[0]:
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r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
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r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
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if dummy_signal:
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r += syn_off
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r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
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r += syn_on
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r += "end\n"
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r += "\n"
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return r
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def _printsync(f, ns):
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r = ""
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for k, v in sorted(f.sync.items(), key=itemgetter(0)):
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r += "always @(posedge " + ns.get_name(f.clock_domains[k].clk) + ") begin\n"
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r += _printnode(ns, _AT_SIGNAL, 1, v)
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r += "end\n\n"
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return r
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def _call_special_classmethod(overrides, obj, method, *args, **kwargs):
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cl = obj.__class__
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if cl in overrides:
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cl = overrides[cl]
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if hasattr(cl, method):
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return getattr(cl, method)(obj, *args, **kwargs)
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else:
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return None
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def _lower_specials_step(overrides, specials):
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f = _Fragment()
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lowered_specials = set()
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for special in sorted(specials, key=lambda x: x.duid):
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impl = _call_special_classmethod(overrides, special, "lower")
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if impl is not None:
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f += impl.get_fragment()
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lowered_specials.add(special)
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return f, lowered_specials
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def _can_lower(overrides, specials):
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for special in specials:
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cl = special.__class__
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if cl in overrides:
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cl = overrides[cl]
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if hasattr(cl, "lower"):
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return True
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return False
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def _lower_specials(overrides, specials):
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f, lowered_specials = _lower_specials_step(overrides, specials)
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while _can_lower(overrides, f.specials):
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f2, lowered_specials2 = _lower_specials_step(overrides, f.specials)
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f += f2
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lowered_specials |= lowered_specials2
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f.specials -= lowered_specials2
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return f, lowered_specials
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def _printspecials(overrides, specials, ns, add_data_file):
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r = ""
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for special in sorted(specials, key=lambda x: x.duid):
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pr = _call_special_classmethod(overrides, special, "emit_verilog", ns, add_data_file)
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if pr is None:
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raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
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r += pr
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return r
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def convert(f, ios=None, name="top",
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special_overrides=dict(),
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create_clock_domains=True,
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display_run=False, asic_syntax=False):
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r = ConvOutput()
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if not isinstance(f, _Fragment):
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f = f.get_fragment()
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if ios is None:
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ios = set()
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for cd_name in list_clock_domains(f):
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try:
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f.clock_domains[cd_name]
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except KeyError:
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if create_clock_domains:
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cd = ClockDomain(cd_name)
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f.clock_domains.append(cd)
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ios |= {cd.clk, cd.rst}
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else:
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raise KeyError("Unresolved clock domain: '"+cd_name+"'")
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f = lower_complex_slices(f)
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insert_resets(f)
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f = lower_basics(f)
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fs, lowered_specials = _lower_specials(special_overrides, f.specials)
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f += lower_basics(fs)
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ns = build_namespace(list_signals(f) \
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| list_special_ios(f, True, True, True) \
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| ios, _reserved_keywords)
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ns.clock_domains = f.clock_domains
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r.ns = ns
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src = "/* Machine-generated using Migen */\n"
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src += _printheader(f, ios, name, ns,
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reg_initialization=not asic_syntax)
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src += _printcomb(f, ns,
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display_run=display_run,
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dummy_signal=not asic_syntax,
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blocking_assign=asic_syntax)
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src += _printsync(f, ns)
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src += _printspecials(special_overrides, f.specials - lowered_specials, ns, r.add_data_file)
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src += "endmodule\n"
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r.set_main_source(src)
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return r
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