Sebastien Bourdeauducq 1857ec6c32 fhdl/namer: support ClockSignal and ResetSignal. Closes #24		2015-09-22 14:30:16 +08:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
bitcontainer.py	fhdl/bitcontainer: remove fiter	2015-09-17 17:22:03 +08:00
conv_output.py	introduce conversion output object (prevents file IO in FHDL backends)	2015-04-08 20:28:23 +08:00
decorators.py	fhdl/decorators: remove traces of deprecated API	2015-09-12 19:44:35 +08:00
edif.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
module.py	simplify imports, migen.fhdl.std -> migen	2015-09-12 19:34:07 +08:00
namer.py	fhdl/namer: support ClockSignal and ResetSignal. Closes #24	2015-09-22 14:30:16 +08:00
simplify.py	sim: memory access from generators	2015-09-20 14:52:26 +08:00
specials.py	sim: memory access from generators	2015-09-20 14:52:26 +08:00
structure.py	fhdl/structure: add missing init	2015-09-20 14:46:30 +08:00
tools.py	fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem	2015-09-15 12:38:02 +08:00
tracer.py	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
verilog.py	fhdl/namer: support ClockSignal and ResetSignal. Closes #24	2015-09-22 14:30:16 +08:00
visit.py	fhdl/visit: support Constant	2015-09-20 16:10:17 +08:00