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litex/migen
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Sebastien Bourdeauducq 1857ec6c32 fhdl/namer: support ClockSignal and ResetSignal. Closes #24
2015-09-22 14:30:16 +08:00
..
build simplify imports, migen.fhdl.std -> migen 2015-09-12 19:34:07 +08:00
fhdl fhdl/namer: support ClockSignal and ResetSignal. Closes #24 2015-09-22 14:30:16 +08:00
genlib genlib/fifo: add missing import 2015-09-19 23:20:19 +08:00
sim sim: insert resets, support ClockSignal and ResetSignal 2015-09-21 22:13:36 +08:00
test sim: VCD output support 2015-09-21 21:20:31 +08:00
util
__init__.py simplify imports, migen.fhdl.std -> migen 2015-09-12 19:34:07 +08:00