sim: memory access from generators
This commit is contained in:
Sebastien Bourdeauducq
parent
59802bec76
commit
320dffb4ac
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@ -7,19 +7,20 @@ class Mem(Module):
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# from 0 to 19.
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self.specials.mem = Memory(16, 2**12, init=list(range(20)))
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def do_simulation(self, selfp):
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# Read the memory. Use the cycle counter as address.
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value = selfp.mem[selfp.simulator.cycle_counter]
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# Print the result. Output is:
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# 0
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# 1
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# 2
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# ...
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def memory_test(dut):
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# write (only first 5 values)
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for i in range(5):
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yield dut.mem[i], 42 + i
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# remember: values are written after the tick, and read before the tick.
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# wait one tick for the memory to update.
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yield
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# read what we have written, plus some initialization data
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for i in range(10):
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value = yield dut.mem[i]
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print(value)
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# Raising StopSimulation disables the current (and here, only one)
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# simulation function. Simulator stops when all functions are disabled.
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if value == 10:
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raise StopSimulation
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if __name__ == "__main__":
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run_simulation(Mem())
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dut = Mem()
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Simulator(dut, memory_test(dut)).run()
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@ -5,6 +5,9 @@ from migen.util.misc import gcd_multiple
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class FullMemoryWE(ModuleTransformer):
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def __init__(self):
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self.replacments = dict()
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def transform_fragment(self, i, f):
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newspecials = set()
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@ -16,6 +19,7 @@ class FullMemoryWE(ModuleTransformer):
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if global_granularity == orig.width:
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newspecials.add(orig) # nothing to do
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else:
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newmems = []
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for i in range(orig.width//global_granularity):
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if orig.init is None:
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newinit = None
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@ -23,6 +27,7 @@ class FullMemoryWE(ModuleTransformer):
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newinit = [(v >> i*global_granularity) & (2**global_granularity - 1) for v in orig.init]
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newmem = Memory(global_granularity, orig.depth, newinit, orig.name_override + "_grain" + str(i))
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newspecials.add(newmem)
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newmems.append(newmem)
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for port in orig.ports:
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port_granularity = port.we_granularity if port.we_granularity else orig.width
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newport = _MemoryPort(
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@ -39,11 +44,15 @@ class FullMemoryWE(ModuleTransformer):
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clock_domain=port.clock)
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newmem.ports.append(newport)
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newspecials.add(newport)
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self.replacments[orig] = newmems
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f.specials = newspecials
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class MemoryToArray(ModuleTransformer):
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def __init__(self):
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self.replacements = dict()
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def transform_fragment(self, i, f):
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newspecials = set()
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@ -53,6 +62,7 @@ class MemoryToArray(ModuleTransformer):
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continue
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storage = Array()
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self.replacements[mem] = storage
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init = []
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if mem.init is not None:
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init = mem.init
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@ -90,6 +100,15 @@ class MemoryToArray(ModuleTransformer):
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# write
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if port.we is not None:
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sync.append(If(port.we, storage[port.adr].eq(port.dat_w)))
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if port.we_granularity:
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n = mem.width//port.we_granularity
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for i in range(n):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity
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sync.append(If(port.we[i],
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storage[port.adr][m:M].eq(port.dat_w)))
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else:
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sync.append(If(port.we,
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storage[port.adr].eq(port.dat_w)))
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f.specials = newspecials
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@ -1,7 +1,7 @@
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from operator import itemgetter
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _DUID
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from migen.fhdl.structure import _DUID, _Value
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from migen.fhdl.bitcontainer import bits_for, value_bits_sign
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from migen.fhdl.tools import *
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from migen.fhdl.tracer import get_obj_var_name
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@ -210,6 +210,18 @@ class _MemoryPort(Special):
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return "" # done by parent Memory object
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class _MemoryLocation(_Value):
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def __init__(self, memory, index):
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_Value.__init__(self)
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if isinstance(index, (bool, int)):
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index = Constant(index)
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if not isinstance(index, _Value):
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raise TypeError("Memory index is not a Migen value: {}"
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.format(index))
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self.memory = memory
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self.index = index
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class Memory(Special):
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def __init__(self, width, depth, init=None, name=None):
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Special.__init__(self)
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@ -219,6 +231,10 @@ class Memory(Special):
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self.init = init
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self.name_override = get_obj_var_name(name, "mem")
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def __getitem__(self, index):
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# simulation only
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return _MemoryLocation(self, index)
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def get_port(self, write_capable=False, async_read=False,
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has_re=False, we_granularity=0, mode=WRITE_FIRST,
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clock_domain="sys"):
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@ -325,7 +341,6 @@ class Memory(Special):
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r += "\t$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
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r += "end\n\n"
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return r
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22
migen/sim.py
22
migen/sim.py
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@ -1,11 +1,12 @@
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import operator
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from migen.fhdl.structure import *
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from migen.fhdl.structure import (_Operator, _Slice, _ArrayProxy,
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from migen.fhdl.structure import (_Value, _Operator, _Slice, _ArrayProxy,
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_Assign, _Fragment)
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from migen.fhdl.bitcontainer import flen
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from migen.fhdl.tools import list_targets
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from migen.fhdl.simplify import FullMemoryWE, MemoryToArray
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from migen.fhdl.simplify import MemoryToArray
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from migen.fhdl.specials import _MemoryLocation
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__all__ = ["Simulator"]
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@ -61,7 +62,8 @@ str2op = {
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class Evaluator:
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def __init__(self):
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def __init__(self, replaced_memories):
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self.replaced_memories = replaced_memories
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self.signal_values = dict()
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self.modifications = dict()
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@ -114,6 +116,9 @@ class Evaluator:
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elif isinstance(node, _ArrayProxy):
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return self.eval(node.choices[self.eval(node.key, postcommit)],
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postcommit)
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elif isinstance(node, _MemoryLocation):
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array = self.replaced_memories[node.memory]
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return self.eval(array[self.eval(node.index, postcommit)], postcommit)
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else:
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# TODO: ClockSignal, ResetSignal
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raise NotImplementedError
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@ -140,6 +145,9 @@ class Evaluator:
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self.assign(node, full_value)
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elif isinstance(node, _ArrayProxy):
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self.assign(node.choices[self.eval(node.key)], value)
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elif isinstance(node, _MemoryLocation):
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array = self.replaced_memories[node.memory]
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self.assign(array[self.eval(node.index)], value)
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else:
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# TODO: ClockSignal, ResetSignal
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raise NotImplementedError
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@ -182,15 +190,15 @@ class Simulator:
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else:
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self.generators[k] = [v]
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FullMemoryWE().transform_fragment(None, self.fragment)
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MemoryToArray().transform_fragment(None, self.fragment)
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mta = MemoryToArray()
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mta.transform_fragment(None, self.fragment)
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# TODO: insert_resets on sync
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# comb signals return to their reset value if nothing assigns them
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self.fragment.comb[0:0] = [s.eq(s.reset)
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for s in list_targets(self.fragment.comb)]
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self.time = TimeManager(clocks)
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self.evaluator = Evaluator()
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self.evaluator = Evaluator(mta.replacements)
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def _commit_and_comb_propagate(self):
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# TODO: optimize
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@ -202,7 +210,7 @@ class Simulator:
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def _eval_nested_lists(self, x):
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if isinstance(x, list):
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return [self._eval_nested_lists(e) for e in x]
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elif isinstance(x, Signal):
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elif isinstance(x, _Value):
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return self.evaluator.eval(x)
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else:
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raise ValueError
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